Specifications

Altera Corporation Software Version 7.1 SP1 11
DSP Builder Release Notes
Upgrading Your Existing Models
The BP block does
not support sample
time mode
A warning is issued if your design includes a Bus Probe (BP) block which was set to
display the sample time because this option is no longer supported.
Phase selection has
been standardized
across all blocks
This may result in behavioral change when upgrading blocks that use phase selection.
The Multi Channel
Display and Extract
blocks are not
supported
These blocks are no longer supported and should be removed before running the
upgrade script. You can use the Avalon-ST Packet Format Converter block directly in
place of these blocks. To prevent HDL being generated, insert Output blocks followed
by Non-synthesizable Input blocks on the inputs to the Avalon-ST Packet Format
Converter block.
HIL designs must be
recompiled
For designs with Hardware in the Loop, you must recreate the Quartus II project and
recompile the HIL revision after upgrading.
Changes to rounding
method used for the
MATLAB arrays used
to initialize the LUT
and RAM blocks
The rounding method used when the data values specified by an initializing MATLAB
array are not exactly expressible in the chosen data type has changed. This means for
example, that if you specified the data type as Unsigned Integer and the value as 1.9 in
a previous release this value was rounded up to 2; in v7.1 it is rounded down to 1.
You should the check the outputs from LUT or RAM blocks if an error is issued stating
that the values cannot be exactly represented in the selected data format and choose
revised initialization values that can be represented exactly if the outputs are not as
expected.
Black box subsystem
are not upgraded
Altbus blocks used as black box inputs or outputs must be manually changed to HDL
Input and HDL Output blocks and a HDL Entity block added to specify the HDL file and
clock/reset ports.
VCD Sink block
supports a maximum
of 10 inputs
Any VCD Sink blocks with >10 inputs must be replaced by separate VCD Sink blocks
with no more than 10 inputs before upgrading.
An error is issued for
any block name which
has a ‘/’ character
Rename any block containing a ‘/’ character in its name.
AltBus blocks within
subsystems which
function as input pins
not updated correctly
Move the input pins to the top level or replace them by Input blocks. (It is better to
replace these AltBus blocks before upgrading to ensure that the clock signals are set
correctly.)
Device Programmer
block is not supported
Remove the Device Programmer block before running the upgrade program. Use Signal
Compiler or a HIL block to program the DSP development board.
The External RAM
block is not upgraded
This block is outside the DSP Builder system and is not automatically updated. You
must manually replace any External RAM blocks in your designs with the v7.1 version.
Table 2. Model Upgrade Issues
Issue Action