Specifications
AD1974 Data Sheet
Rev. D | Page 6 of 24
Parameter Condition Comments Min Max Unit
PLL
Lock Time MCLK and LRCLK input 10 ms
256 f
S
VCO Clock 40 60 %
Output Duty Cycle
MCLK_O Pin
SPI PORT See Figure 5
t
CCH
CCLK high 35 ns
t
CCL
CCLK low 35 ns
f
CCLK
CCLK frequency f
CCLK
= 1/t
CCP
; only t
CCP
shown in Figure 5
10 MHz
t
CDS
CDATA setup To CCLK rising 10 ns
t
CDH
CDATA hold From CCLK rising 10 ns
t
CLS
Setup To CCLK rising 10 ns
t
CLH
Hold From CCLK rising 10 ns
t
CLHIGH
High Not shown in Figure 5 10 ns
t
COE
COUT enable From CCLK falling 30 ns
t
COD
COUT delay From CCLK falling 30 ns
t
COH
COUT hold From CCLK falling, not shown in Figure 5 30 ns
t
COTS
COUT tristate From CCLK falling 30 ns
ADC SERIAL PORT See Figure 13
t
ABH
ABCLK high Slave mode 10 ns
t
ABL
ABCLK low Slave mode 10 ns
t
ALS
ALRCLK setup
To ABCLK rising, slave mode
10
ns
t
ALH
ALRCLK hold From ABCLK rising, slave mode 5 ns
t
ALS
ALRCLK skew From ABCLK falling, master mode −8 +8 ns
t
ABDD
ASDATA delay From ABCLK falling 18 ns
AUXILIARY INTERFACE See Figure 12
t
XDS
AAUXDATA setup To AUXBCLK rising 10 ns
t
XDH
AAUXDATA hold From AUXBCLK rising 5 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
XLS
AUXLRCLK setup
To AUXBCLK rising
10
ns
t
XLH
AUXLRCLK hold From AUXBCLK rising 5 ns