Datasheet

[AK4646]
MS0557-E-06 2011/06
- 75 -
■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1.
PLL Master Mode
External MCKI
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
Input
(3)
(1)
(2)
"0" or "1"
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(3) Stop an external MCKI
(1) (2) Addr:01H, Data:08H
Figure 46. Clock Stopping Sequence (1)
<Example>
(1)
Power down PLL: PMPLL bit = “1” → “0”
(2)
Stop MCKO clock: MCKO bit = “1” → “0”
(3)
Stop an external master clock.
2.
PLL Slave Mode (LRCK or BICK pin)
External BICK
PMPLL bit
(Addr:01H, D0)
Input
(1)
(2)
External LRCK Input
(2)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 47. Clock Stopping Sequence (2)
<Example>
(1)
Power down PLL: PMPLL bit = “1” → “0”
(2)
Stop the external BICK and LRCK clocks