Datasheet

[AK4646]
MS0557-E-06 2011/06
- 57 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Signal Select 2 DAFIL LOPS
MGAIN1
SPKG1 SPKG0 BEEPL LOVL1 LOVL0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
LOVL1-0: Output Stereo Line Gain Select (
Table 41)
Default: 00(0dB)
BEEPL: Switch Control from MIN pin to Stereo Line Output
0: OFF (default)
1: ON
When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.
SPKG1-0: Speaker-Amp Output Gain Select (
Table 43)
MGAIN1: MIC-Amp Gain Control (
Table 19)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (default)
1: Power-Save Mode
DAFIL: Filter/ALC Path Select When PMADL bit = “1” or PMADR bit = “1”
0: ADC/Recording Path (default)
1: DAC/Playback Path
The SDTO pin outputs “L” with regardless of PMADL and PMADR bits when DAFIL bit = “1” and
PMDAC bit = “1”.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0
R/W R/W R/W R/W R/W R/W R R/W R/W
Default 0 0 0 0 0 0 1 0
DIF1-0: Audio Interface Format (
Table 16)
Default: “10” (Left justified)
BCKO: BICK Output Frequency Select at Master Mode (
Table 10)
PLL3-0: PLL Reference Clock Select (
Table 4)
Default: “0000” (LRCK pin)
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0
R/W R/W R/W R/W R R R/W R/W R/W
Default 0 0 0 0 0 0 0 0
FS3-0: Sampling Frequency Select (
Table 5 and Table 6) and MCKI Frequency Select (Table 11)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
PS1-0: MCKO Output Frequency Select (
Table 9)
Default: “00” (256fs)