Datasheet

[AK4646]
MS0557-E-06 2011/06
- 52 -
■ Serial Control Interface
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Each bit is
clocked in on the rising edge (“
↑”) of CCLK. It is available for writing data on the rising edge of CSN. When reading
operation, CDTIO pin has become an output mode at the falling edge of 8
th
CCLIC and outputs D7-D0. The output
finishes on the rising edge of CSN. The CDTIO is placed in a Hi-Z state except outputting data at read operation mode.
Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”.
Note 41. It is available for reading the address 00H~11H. When reading the address 12H
∼ 7FH, the register values are
invalid.
CSN
CCLK
0
1
2
3 4 5
6 7 8 9 10 11
12 13 14 15
CDTIO
A6 A5 A2 A3 A1 A0 A4 D7 D6 D5 D4 D3 D2 D1 D0
R/W
R/W: READ/WRITE (“1”: WRITE, “0”: READ)
A6-A0: Register Address
D7-D0: Control data (Input) at Write Command
Output data (Output) at Read Command
“H” or “L” “H” or “L”
“H” or “L” “H” or “L”
Figure 36. Serial Control I/F Timing