Datasheet

[AK4646]
MS0557-E-06 2011/06
- 48 -
[Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)]
PMLO bit
LO PS bit
LOUT, ROUT pins
(1)
(2)
Norm al Output
(3) (4)
(5)
(6)
≥ 300 m s ≥ 300 m s
Figure 33. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)
(1)
Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2)
Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1
μF.
(3)
Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4)
Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5)
Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1
μF.
(6)
Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.