Datasheet

[AK4646]
MS0557-E-06 2011/06
- 47 -
■ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10k
Ω
(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is
pulled-down to AVSS by 100k
Ω(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be
pulled-down to AVSS by 20k
Ω after AC coupled as Figure 32. Rise/Fall time is 300ms (max) at C=1μF. When PMLO bit
= “1” and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
DAC
“DACL”
LOUT pin
ROUT pin
“LOVL”
Figure 31. Stereo Line Output
LOPS PMLO Mode LOUT/ROUT pin
0 Power-down Pull-down to AVSS (default)
0
1 Normal Operation Normal Operation
0 Power-save Fall down to AVSS
1
1 Power-save Rise up to VCOM
Table 40. Stereo Line Output Mode Select (x: Don’t care)
LOVL1-0 bits Gain
00 0dB (default)
01 +2dB
10 +4dB
11 +6dB
Table 41. Stereo Line Output Volume Setting
LOUT
ROUT
1
μ
F
220
Ω
20k
Ω
Figure 32. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)