Datasheet

[AK4646]
MS0557-E-06 2011/06
- 42 -
fs=8kHz fs=44.1kHz
Register Name Comment
Data Operation Data Operation
LMTH1-0 Limiter detection Level 01
−4.1dBFS
01
−4.1dBFS
ZELMN Limiter zero crossing detection 0 Enable 0 Enable
ZTM1-0 Zero crossing timeout period 01 32ms 11 23.2ms
WTM2-0
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
001 32ms 100 46.4ms
OREF5-0 Maximum gain at recovery operation 28H +6dB 28H +6dB
OVL7-0,
OVR7-0
Gain of VOL 91H 0dB 91H 0dB
LMAT1-0 Limiter ATT step 00 1 step 00 1 step
LFST Fast Limiter Operation 1 ON 1 ON
RGAIN1-0 Recovery GAIN step 00 1 step 00 1 step
RFST1-0 Fast Recovery Speed 00 4 times 00 4 times
ALC2 ALC enable 1 Enable 1 Enable
Table 33. Example of the ALC Setting (Playback)
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST
Manual Mode
* The value of IVOL should be
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0)
WR (IREF7-0)
WR (IVL/R7-0)
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level =
−
4.1dBFS
ALC bit = “1”
(1) Addr=06H, Data=14H
(2) Addr=08H, Data=E1H
(5) Addr=07H, Data=21H
(3) Addr=09H&0CH, Data=E1H
ALC Operation
WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=28H
Note : WR : Write
Figure 29. Registers set-up sequence at ALC operation