Datasheet

[AK4646]
MS0557-E-06 2011/06
- 29 -
LRCK
BICK(32fs)
SDTO(o)
SDTI(i)
0
15 14
15 14
110
23
7
76543
210
6543
102
9 1112131415 0
123
15 14
10
76543210
109 1112131415
BICK(64fs)
0 1162 3 17 18 31 0 1 2 3 1016 17 18 31
SDTO(o)
SDTI(i)
15 14
Don't Care
2
15
1
15
15
15 Don't Care
15:MSB, 0:LSB
Lch Data Rch Data
14 21 14 21
8
8
80
0
0 0
0 15 14 765432108
15 14 210
Figure 20. Mode 3 Timing
■ Mono/Stereo Mode
PMADL and PMADR bits set mono/stereo ADC operation.
When changing ADC operation, PMADL and PMADR bits should be set “0” at first.
PMADL bit PMADR bit ADC Lch data ADC Rch data
0 0 All “0” All “0” (default)
0 1 Rch Input Signal Rch Input Signal
1 0 Lch Input Signal Lch Input Signal
1 1 Lch Input Signal Rch Input Signal
Table 17. Mono/Stereo ADC operation