Datasheet

[AK4646]
MS0557-E-06 2011/06
- 22 -
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK
clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (
Table 9) and the
output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (
Table 10).
AK4646
DSP or μP
MCKO
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKI
1fs
32fs, 64fs
256fs/128fs/64fs/32fs
12MHz, 13.5MHz, 24MHz, 27MHz
MCLK
Figure 12. PLL Master Mode
Mode PS1 bit PS0 bit MCKO pin
0 0 0 256fs (default)
1 0 1 128fs
2 1 0 64fs
3 1 1 32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO bit
BICK Output
Frequency
0 32fs (default)
1 64fs
Table 10. BICK Output Frequency at Master Mode