Datasheet

[AK4646]
MS0557-E-06 2011/06
- 16 -
1/fCLK
MCKI
tCLKH tCLKL
VIH
VIL
1/fs
LRCK
VIH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
tLRCKH tLRCKL
fMCK
MCKO
tMCKL
50%DVDD
dMCK = tMCKL x fMCK x 100
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
Figure 4. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
1/fCLK
MCKI
tCLKH tCLKL
VIH
VIL
1/fs
LRCK
VIH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
tLRCKH tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
Figure 5. Clock Timing (EXT Slave mode)