Datasheet

[AK4646]
MS0557-E-06 2011/06
- 15 -
■ Timing Diagram
LRCK
1/fCLK
MCKI
tCLKH tCLKL
VIH
VIL
1/fMCK
MCKO
tMCKL
50%DVDD
1/fs
tLRCKH tLRCKL
50%DVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
dMCK = tMCKL x fMCK x 100
Note 31. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL / EXT Master mode)
LRCK
50%DVDD
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI
VIL
tSDH
VIH
tBLR
tBCKL
tDLR
Figure 3. Audio Interface Timing (PLL/EXT Master mode)