Datasheet

[AK4646]
MS0557-E-06 2011/06
- 14 -
Parameter Symbol min typ max Units
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (
Note 27)
tMBLR
−40
- 40 ns
LRCK Edge to SDTO (MSB)
(Except I
2
S mode)
tLRD
−70
- 70 ns
BICK “↓” to SDTO
tBSD
−70
- 70 ns
SDTI Hold Time tSDH 50 - - ns
SDTI Setup Time tSDS 50 - - ns
Slave Mode
LRCK Edge to BICK “↑” (
Note 27)
tLRB 50 - - ns
BICK “↑” to LRCK Edge (
Note 27)
tBLR 50 - - ns
LRCK Edge to SDTO (MSB)
(Except I
2
S mode)
tLRD - - 80 ns
BICK “↓” to SDTO
tBSD - - 80 ns
SDTI Hold Time tSDH 50 - - ns
SDTI Setup Time tSDS 50 - - ns
Control Interface Timing
CCLK Period tCCK 200 - - ns
CCLK Pulse Width Low tCCKL 80 - - ns
Pulse Width High tCCKH 80 - - ns
CDTIO Setup Time tCDS 40 - - ns
CDTIO Hold Time tCDH 40 - - ns
CSN “H” Time tCSW 150 - - ns
CSN Edge to CCLK “↑” (
Note 28)
tCSS 50 - - ns
CCLK “↑” to CSN Edge (
Note 28)
tCSH 50 - - ns
CCLK “↓” to CDTIO (at Read Command)
tDCD - - 70 ns
CSN “↑” to CDTIO (Hi-Z) (at Read Command)
tCCZ - - 70 ns
Power-down & Reset Timing
PDN Pulse Width (
Note 29) tPD 150 - - ns
PMADL or PMADR “↑“ to SDTO valid
(
Note 30) tPDV - 1059 - 1/fs
Note 27. BICK rising edge must not occur at the same time as LRCK edge.
Note 28. CCLK rising edge must not occur at the same time as CSN edge.
Note 29. The AK4646 can be reset by the PDN pin = “L”.
Note 30. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.