Datasheet

[AK4646]
MS0557-E-06 2011/06
- 13 -
Parameter Symbol min typ max Units
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency fs 7.35 - 48 kHz
Duty Duty 45 - 55 %
BICK Input Timing
Period tBCK 1/(64fs) - 1/(32fs) ns
Pulse Width Low tBCKL 240 - - ns
Pulse Width High tBCKH 240 - - ns
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency fs 7.35 - 48 kHz
Duty Duty 45 - 55 %
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK - 1/(32fs) - ns
PLL3-0 bits = “0011”
tBCK - 1/(64fs) - ns
Pulse Width Low tBCKL 0.4 x tBCK - - ns
Pulse Width High tBCKH 0.4 x tBCK - - ns
External Slave Mode
MCKI Input Timing
Frequency 256fs fCLK 1.8816 - 12.288 MHz
512fs fCLK 3.7632 - 13.312 MHz
1024fs fCLK 7.5264 - 13.312 MHz
Pulse Width Low tCLKL 0.4/fCLK - - ns
Pulse Width High tCLKH 0.4/fCLK - - ns
LRCK Input Timing
Frequency 256fs fs 7.35 - 48 kHz
512fs fs 7.35 - 26 kHz
1024fs fs 7.35 - 13 kHz
Duty Duty 45 - 55 %
BICK Input Timing
Period tBCK 312.5 - - ns
Pulse Width Low tBCKL 130 - - ns
Pulse Width High tBCKH 130 - - ns
External Master Mode
MCKI Input Timing
Frequency 256fs fCLK 1.8816 - 12.288 MHz
512fs fCLK 3.7632 - 13.312 MHz
1024fs fCLK 7.5264 - 13.312 MHz
Pulse Width Low tCLKL 0.4/fCLK - - ns
Pulse Width High tCLKH 0.4/fCLK - - ns
LRCK Output Timing
Frequency fs 7.35 - 48 kHz
Duty Cycle Duty - 50 - %
BICK Input Timing
Period BCKO bit = “0” tBCK - 1/(32fs) - ns
BCKO bit = “1” tBCK - 1/(64fs) - ns
Duty Cycle dBCK - 50 - %