Specifications

Appendix B
Implementation details
In this section we give the basic information on how the synchronization method is imple-
mented.
The synchronization setup at each site (local group of nearby nodes) of the measured
network is the same. We have one ”master” node which hosts a GPS card and a master
clock card. All the other nodes only host a slave clock card. There are some hardware
differences between the master and slave clock cards - see Catalin’s log book for detail. The
firmware is the same on all cards. T he slave cards can be replaced by master cards but the
reverse is not possible.
Each clock card has three inputs and one output. Two of the inputs are the 10MHz and
the 1Hz pulses from the GPS which are distributed using T connectors. The last input is
used to receive ”w rite down” commands from the m aster and is also distributed using T
connectors. The output is used to send ”write down” commands and is only connected on
the clock card in the ”master” node. It is then transmitted to the ”write down” input of
the same card then sent to all the other cards. The ”master” card is the only one having
the ability of sending signals on the ”write down” wire. Its inputs are also terminated, so
they should be the last to be reached by the signal.
On all the no des in a local group there is a program waiting for commands on a TCP/IP
port. On the ”master” node there will be a ”driver” program which will command the
computers – in fact we need to command the clock boards in the computers, but the easiest
way is to do so is through the host computers. Also two kernel modules are used - one for
the GPS card and one for the clock card.
B.1 Clock boards
B.1.1 Hardware
The clock board hardware was designed and manufactured at CERN. It contains a FPGA
chip - ALTERA Flex 10k - that is programmed using the Handel-C / VHDL languages.
The board has 4 ports (connectors) that can be configured as inputs or outputs using some
jumpers on the board. The behavior of the card and its I/O features are completely defined
by the firmware from the FPGA.
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