Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-59
Configuration Registers
18:16 RW 0
Count Event Select
This field determines the counter enable source.
000 PME register event
001 Partner event status (max compare or overflow)
010 All clocks when enabled
011 Reserved
100 EV0 pin
101 EV1 pin
110 EV2 pin
111 EV3 pin
15:14 RW 0
Count Mode
00 = count event selected by Count Event Select field.
01 = count clocks after event selected by Count Event Select field.
10 = count transaction length of event, selected by SPPME register.
11 = Reserved
13:12 RW 0
Event Status
This status bit captures an overflow or count compare event. The Event
Status Output field can be programmed to allow this bit to be driven to an
external EV pin.
00 - no event
x1 - overflow – The PMD counter overflow status. (Write’0’ or start an interval
to clear.)
1x - count compare – PMD counter greater than PMC register when in
compare mode. (Write’0’ or start an interval to clear.)
This bit is sticky in that once an event is reported the status remains even
though the original condition is no longer valid. This bit can be cleared by
software or by starting a sample. Event status is always visible in the
PERFCON register, except if Event Status Output field is in cascade mode.
If in address compare mode (compare mode = 11), the count compare bit is
not activated.
11:9 RW 0
Event Status Output
This field selects where the event status is reported.
000 Event status reported only in PERFCON register
(address comparison not reported)
001 Event status (overflow) reported to partner only;
used for cascading event counters
100 Event status or address comparison on PERFCON and EV0 pin
101 Event status or address comparison on PERFCON and EV1 pin
110 Event status or address comparison on PERFCON and EV2 pin
111 Event status or address comparison on PERFCON and EV3 pin
8:5 RW 0
CD_Src: Counter Disable Source
These bits control which input disables the counter.
Note: If the “Enable Source” is inactive counting is also disabled.
1xxx EV3 pin
x1xx EV2 pin
xx1x EV1 pin
x x1x EV0 pin
Device: NodeID
Function: 2
Offset: E0h (SPPMR0), F0h(SPPPMR1) (Continued)
Bit Attr Default Description