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Intel

E8870 Scalable Node Controller

(SNC) Datasheet

Product Features

■ Intel

Itanium

2 Processor System Bus

— Itanium 2 processor system bus

interface (44-bit address, 128-bit data)

at 400 MHz data bus frequency

— Full multiprocessor support for up to

four Itanium 2 processors on the system

bus

— Parity protection on address and control

signals

— ECC protection on each 64-bit chunk of

the 128-bit data signals on the

Itanium 2 processor system bus

— Eight-deep in-order queue

— Non-blocking transaction handling::

Transactions receive Normal

Completion, Retry, or Defer;

All transactions normally deferred;

No chipset snoop stalls

— GTL+ bus driver technology

— Chipset adds only one load to the

system bus

■ PC1600 DDR SDRAM Memory via DDR

Memory Hub (DMH)

— Supports up to four DMHs

— 1, 2, 3, or 4 different types of DIMMs

per branch channel

— Supports 128-, 256-, 512-, 1024-Mb

devices in X4 and X8 configurations

— Supports from 512 MB (128 Mb

devices) to 128 GB (1 Gb devices) of

memory in 128 MB increments

— 6.4 GB/s peak bandwidth

— Server Error Correction Code corrects

for any single failed X4 memory

device, and limited correction on data

errors from X8 memory devices

— ECC with error correction and periodic

scrubbing of the memory

■ Scalability Port (SP)

— Two SPs with 3.2 GB/s peak bandwidth

per direction per SP

— Bidirectional SPs for a total bandwidth

of 12.8 GB/s

■ Firmware

— Firmware hub interface for processor-

specific firmware

■ Reliability, Availability, and Serviceability

(RAS)

— Sideband access to configuration

registers via SMBus or JTAG.

— End-to-end ECC for all interfaces

— Fault detection and logging

— Signal connectivity testing via

boundary scan

■ Packaging

— 49.5mm x 49.5mm

— 1357-pin organic LAN grid array

(OLGA) package-2B

Document Number: 251112-001

August 2002

Summary of content (240 pages)

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Intel® E8870 Scalable Node Controller (SNC) Datasheet Product Features ■ ■ Intel® Itanium® 2 Processor System Bus — Itanium 2 processor system bus interface (44-bit address, 128-bit data) at 400 MHz data bus frequency — Full multiprocessor support for up to four Itanium 2 processors on the system bus — Parity protection on address and control signals — ECC protection on each 64-bit chunk of the 128-bit data signals on the Itanium 2 processor system bus — Eight-deep in-order queue — Non-blocking transactio
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.
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Contents 1 Introduction......................................................................................................................1-1 1.1 Overview ............................................................................................................1-1 1.2 Scalable Node Controller (SNC) Overview ........................................................1-1 1.3 Architectural Overview .......................................................................................1-3 1.4 Interfaces.....
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3.7 3.8 3.9 3.10 iv 3.6.8 SMRAM: SMM RAM Control Register.................................................3-11 3.6.9 MIR[9:0]: Memory Interleave Range Registers ...................................3-12 Memory Controller Registers ...........................................................................3-13 3.7.1 MC: Memory Control Settings .............................................................3-13 3.7.2 MIT[9:0]: Memory Interleave Technology Registers............................3-14 3.7.
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3.10.11 FSBPMEU[1:0]: Processor Bus Perform Monitor Utilization Events.................................................................................3-55 3.10.12 SPPMD[1:0]: SP Performance Monitor Data.......................................3-57 3.10.13 SPPMC[1:0]: SP Performance Compare ............................................3-57 3.10.14 SPPMR[1:0]: SP Performance Monitor Response ..............................3-58 3.10.15 SPPME[1:0]: SP Performance Monitor Events ...................................
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Reliability, Availability, and Serviceability........................................................................ 6-1 6.1 Data Integrity...................................................................................................... 6-1 6.1.1 End-to-end Error Correction ..................................................................6-5 6.1.2 Data Poisoning ......................................................................................6-6 6.1.3 Error Reporting..........................
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8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.3.17 8.3.18 P64H2: RSTIN#...................................................................................8-15 SNC: RESETO# ..................................................................................8-15 SNC: RESET# and Processor Power-on Configuration......................8-15 SNC and DMH: MEMRST# .................................................................8-15 SNC and DMH: R[3:0]SCK,R[3:0]SIO,R[3:0]CMD ....................
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Figures 1-1 1-2 1-3 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 9-1 9-2 9-3 9-4 10-1 10-2 10-3 11-1 11-2 11-3 11-4 viii Typical Itanium® 2-Based Server Configuration.................................................1-2 Scalable Node Controller Queueing Structures .................................................1-3 Scalable Node Controller Interfaces ..................................................................1-4 System Memory Address Space.....................
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Tables 1-1 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 Chipset Component Markings ............................................................................1-1 Buffer Technology Types ...................................................................................2-1 Buffer Signal Directions..................................................................
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9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 10-1 10-2 11-1 11-2 11-3 11-4 x RAMBUS “CMOS 1.8 I/O” DC Parameters ........................................................9-6 LPC Interface Signal Group ...............................................................................9-7 LPC DC Parameters ..........................................................................................9-7 SMBus and TAP Interface Signal Group....
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1 Introduction 1.1 Overview The Intel® E8870 chipset delivers new levels of availability, features and performance for servers. It provides flexible common modular architecture support for the Intel® Itanium® 2 processors. The Intel E8870 chipset supports up to four processors, and up to eight processors with the Scalability Port Switch (SPS) component, delivering stability to the platforms through reuse and common architecture support.
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Introduction Figure 1-1. Typical Itanium® 2-Based Server Configuration Itanium ® 2 Processor Itanium ® 2 Processor Itanium ® 2 Processor Itanium ® 2 Processor SNC (Scalable Node Controller) Flash BIOS Itanium ® 2 Processor Flash BIOS Memory SP (Scalability Port) Switch SIOH (Serv er Input/Output Hub) HI 1.
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Introduction 1.3 Architectural Overview Figure 1-2 is a conceptual depiction of the SNC’s queueing structures. The system bus logic includes the In Order Queue (IOQ) that tracks pipelined in order transactions. Figure 1-2.
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Introduction 1.4 Interfaces Figure 1-3 illustrates the SNC and all of its interfaces, which consist of the processor system bus, four main channels, a firmware hub interface, two scalability ports as well as JTAG and SMBus ports. The processor system bus interfaces with one to four processors. The two SPs interface to the scalability port switch or SIOH. Each of the main channels interface to the DMH for DDRSDRAM support. Figure 1-3. Scalable Node Controller Interfaces Itanium® 2 Processor 400 MHz 6.
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Introduction A clock generator must be provided for each channel that is compliant with the Direct RAMBUS Clock Generator Specification. The SNC will provide a pair of clock phase references for each of the four main channels. An external clock generator will use these references to generate the 400 MHz differential clock to master (CTM) so that it arrives at the SNC co-incident with the SNC core clock. 1.4.
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Introduction 1.4.6 SMBus Slave Interface This port is controlled by an autonomous platform manager during system operation. The chipset will support serial data transfers at 100 kHz. The chipset is designed to limit the worst case probability of metastability on SMBus command transfers to less than one in 1011. 1.
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Introduction Implicit Write-Back (IWB) IWB is used to describe the hit-modified-snoop response to a processor bus request. Although this is a response, it modifies the handling of the original read. The new behavior is independent of the original read type. In effect, the SNC converts the original request into an IWB. A hit to a modified line in the SIOH can also be called an IWB.
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Introduction 1.6 SNC Scalable Node Controller. This chipset component interface with the Itanium 2 processor, main memory, and SP links. SPS Intel E8870SP Scalability Port Switch. The crossbar/central snoop filter that connects the SNCs and SIOHs. SPP Scalability Port Protocol Logic. The SNC cluster that controls sequencing of coherent requests. SSO Simultaneous Switching Output System Bus A generic term used to refer to the Itanium 2 processor system bus (128 bits wide).
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2 Signal Description 2.1 Conventions The terms assertion and deassertion are used extensively when describing signals, to avoid confusion when working with a mix of active-high and active-low signals. The term assert, or assertion, indicates that the signal is active, independent of whether the active level is represented by a high or low voltage. The term deassert, or deassertion, indicates that the signal is inactive. Signal names may or may not have a “#” appended to them.
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Signal Description Table 2-2. Buffer Signal Directions Buffer Direction Description I Input signal. O Output signal. OD Output open drain. I/O Bidirectional (input/output) signal. SBD Simultaneous Bi-directional signal. Some signals or groups of signals have multiple versions. These signal groups may represent distinct but similar ports or interfaces, or may represent identical copies of the signal used to reduce loading effects. Table 2-3 shows the conventions SNC use. Table 2-3.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description Main Channels 0, 1, 2, 3 (continued) R{0/1/2/3}EXCC O RSL 800 MHz Column Expansion Signal These signals are not used by SNC. R{0/1/2/3}CTM I RSL 400 MHz Clock to Master One of the two differential transmit clock signals used for RDRAM operations on the corresponding RAMBUS channel. It is input to SNC and is generated by an external clock generator.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description Scalability Port 0, 1 (continued) SP{0/1}ASTBN[1:0] SP{0/1}AD[15:0] I/O SBD I/O SBD 400 MHz 800 MHz N Strobes Negative phase data strobes for strand A to transfer data at the 2x rate (800 MHz) Data Bus 16 bits of the data portion of a phit on strand A. These bits are SSO encoded. SP{0/1}ASSO determines if these are out of an inverter or not. SP{0/1}BD[15:0]=DATA[31:16].
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description Scalability Port 0, 1 (continued) SP{0/1}GPIO[1:0] I/O CMOS1.5 OD N/A Scalability Port General Purpose I/O These pins are asynchronous open drain I/O signals. To filter glitches on the inputs, the value of the input only changes when the same value has been sampled over four consecutive 200 MHz clock cycles.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description Performance, Debug, and Error Signals (continued) BusID Strap bits that indicate the configuration bus number of this SNC. These bits are captured by the CBC register on the rising edge of RESETI#. The captured value is sent on the IDLE flits. BUSID[2:0] / DBG[7:5]# I/O CMOS1.5 N/A For E8870 chipset systems, BusID should always be set to “111”.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description Clocking 200 MHz Bus Clock This is one of the two differential reference clock inputs to the Phase Locked Loop (PLL) in the SNC core. The circuit board transmission line driving this signal must be delay-matched to the corresponding processor clock signal generated by the system board logic.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description Reset (continued) MEMRST0# O CMOS1.8 N/A Memory Subsystem Reset This signal is asserted by SNC to reset the DMHs (DDR Memory Hubs). It is pulsed just after the deassertion of RESETI#. This is pulsed on every SNC RESETI# deassertion. MEMRST1# O CMOS1.8 N/A Memory Subsystem Reset This is the same as MEMRST0#. This is used so that MEMRST0# is not overloaded. Bit 0 :ITPODTDIS# COMPCNTRL[1:0]# I CMOS1.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description ® Itanium 2 Processor Bus A[43:3]# I/O AGTL+ 200 MHz Address Signals Processor Address Bus. During processor cycles these are inputs. SNC drives A[43:3]# for transactions originating from SP and for deferred reply transactions. ADS# I/O AGTL+ 200 MHz Address/Data Strobe Indicates the first cycle of any request phase. This signal is driven and sampled by SNC.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description ® Itanium 2 Processor Bus (continued) DEP[15:0]# I/O AGTL+ 400 MHz Data Bus ECC ECC coverage for 128 bits of data. SNC generates this ECC when it drives data during the Data phase. SNC also checks ECC for incoming data. DRDY# I/O AGTL+ 200 MHz Data Ready Indicates that data is valid on the data bus during any cycle DRDY# is asserted. SNC asserts DRDY# for each valid data transfer.
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Signal Description Table 2-4. SNC Signal List (Continued) Signal Type Frequency Description ® Itanium 2 Processor Bus (continued) STBN[7:0]# I/O AGTL+ 200 MHz Data Strobes Used to transfer data at the 2x rate. STBn[7:0]# is the negative phase data strobe. Data transfer occurs when the voltage levels of STBn and STPp are equal. SNC drives and samples STBn[7:0]#. STBP[7:0]# I/O AGTL+ 200 MHz Data Strobes Used to transfer data at the 2x rate. STBp[7:0]# is the positive phase data strobe.
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Signal Description 2-12 Intel® E8870 Scalable Node Controller (SNC) Datasheet
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3 Configuration Registers 3.1 Access Mechanisms The SNC configuration registers can be accessed from the following sources: • Configuration Read and Write from either scalability port (SP) • System Management Bus (SMBus) • JTAG : Table 3-1. Register Attributes Definitions Abbreviation Attribute 3.2 Description Read Only RO The bit is set by the hardware only and software can only read the bit. Writes to the register have no effect. A hard reset will set the bit to its default value.
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Configuration Registers 3.2.1 SPADA: Scratch Pad Alias This is a memory mapped alias of the register described in Section 3.8.4, “SPAD: Scratch Pad.” This register may be read or written only by 4-byte accesses. Memory Address:FE60_C400h 3.2.2 Bit Attr Default 31:0 RW 0 Description Scratch pad for system. SPADSA: Sticky Scratch Pad Alias This is a memory mapped alias of the register described in Section 3.8.5, “SPADS: Sticky Scratch Pad.
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Configuration Registers 3.2.6 CBCA3: Chip Boot Configuration Alias This register may be read or written only by 4-byte accesses. Memory Address:FE62_7C00h Bits 95:64 of the register described in Section 3.8.7. 3.3 SNC I/O Space Registers 3.3.1 CFGADR: Configuration Address Register CFGADR is written only when a processor I/O transaction to CF8 is: • Referenced as a Dword. • The Bus Number field matches the Bus field in the CBC register.
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Configuration Registers 3.3.2 CFGDAT: Configuration Data Register CFGDAT provides data for the four bytes of configuration space defined by CFGADR. This register is only accessed if there is an access to I/O address CFCh on the processor bus and CFGADR.CFGE is set. The byte enables with the I/O access define how many configuration bytes are accessed. I/O Address:CFCh Bit Attr Default 31:0 RW 0 Description Configuration Data Window 3.
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Configuration Registers 3.5.2 DID: Device Identification Register This register combined with the Vendor Identification register uniquely identifies the SNC. Writes to this register have no effect. Device: NodeID Function: 0,1,2,3 Offset: 02 - 03h Bit Attr Default Description Device Identification Number Identifies each function of the SNC. 15:0 3.5.
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Configuration Registers 3.5.4 RID: Revision Identification Register This register contains the revision number of the SNC. Device: NodeID Function: 0,1,2,3 Offset: 08h Bit Attr Default Description Revision Identification Number 7:0 3.5.5 RO See Description 00h = A0 stepping 01h = A1 stepping 02h = A2 stepping 03h = A3 stepping 10h = B0 stepping 20h = C0 stepping HDR: Header Type Register This register identifies the header layout of the configuration space.
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Configuration Registers 3.5.7 SID: Subsystem Identity This register identifies the system. Device: Node_ID Function: 0, 1, 2, 3 Offset: 2Eh Bit Attr 15:0 RWO Default Description Subsystem Identification Number 8086h The default value specifies Intel as the system ID for the SNC. Each byte of this register will be writable once. Second and successive writes to a byte will have no effect. 3.6 Address Mapping Registers 3.6.
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Configuration Registers Table 3-3.
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Configuration Registers Processor requests to this space are directed to a particular SP port as a function of the SPINCO and AGP1 registers. This routing forces a single path to each Memory Mapped I/O location. This enables writes to be pipelined while maintaining sequential order. Processor requests to this range are non-coherent. Non-coherent Read/Write are issued on the SP.
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Configuration Registers 3.6.5 AGP1: Advanced Graphics Port Sub-Range 1 Register In general, transactions to the High and Low MMIO range are routed out the default SP. This register defines a sub-range within either the High or Low MMIO range, which is routed out the non-default SP to balance loading. An enabled AGP1 range must be configured to fall within either the High or Low MMIO range (see Section 3.6.3, “MMIOH: High Memory Mapped I/O Space Register” and Section 3.6.
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Configuration Registers Device: NodeID Function: 0 Offset: 50h Bit Attr Default 31:18 RV 0 17:0 RW 0 Description Reserved BASE 3.6.7 Defines the lower limit of MMCFG range. These bits are compared against A[43:26]. If less than 40h, this range is disabled. IORD: I/O Redirection Register This register is used to redirect I/O segments to the compatibility PCI bus. Certain I/O addresses (e.g. MDA,VGA,CFC/CF8) are not redirected according to this register. Section 4.3.2.
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Configuration Registers 3.6.9 MIR[9:0]: Memory Interleave Range Registers These registers define 10 ranges in which all the main memory supported by this SNC falls. Collectively, all the MIRs that cover a range and the Memory Interleave Technology (MIT) associated with them define a cache line interleave. The cache line interleave is the repeating sequence of channels, devices, and internal banks over which a linear stream of cache line accesses cycle.
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Configuration Registers Device: NodeID Function: 1 Offset: 60h,64h,68h,6Ch,70h,74h,78h,7Ch,C4h,C8h (Continued) Bit Attr Default Description WAYS If the bit in this field selected by A[8:7] is set, the access is sent to the devices described by the corresponding MIT register. Each way bit of every Memory Interleave Range must be set in exactly one MIR.
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Configuration Registers Device: NodeID Function: 1 Offset: 40h (Continued) Bit Attr Default Description MECBD: Memory Error Correction Bypass Disable 6 RW 0 = Normal Operation: Correction path is not taken unless correction is required. 1 = All data is forced through the correction path. 0 MECE: Memory Error Correction Enable 0 = No memory read errors are corrected. Logging is unaffected, but poisoning will not occur. Good SEC/DED will be generated for all memory reads.
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Configuration Registers Table 3-4. MIT Definition for DDR SDRAM (Continued) Device: NodeID Function: 1 Offset: A0h,A4h,A8h,ACh,B0h,B4h,B8h,BCh,CCh,D0h (Continued) Bit Attr Default Description RAFIX 13:11 RW 0 This field defines which portion of the DIMM is mapped by this register. This is accomplished by assigning fixed values to the most significant Row address bits for this technology. The same half or quarter of a DIMM should not be mapped by different MITs.
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Configuration Registers A MIT may not describe more than one DIMM. Multiple MITs can apply to the same DIMM if the associated MIR registers define different address ranges. The DMH specifies the correlation between CS to SPD address bits on DIMMs and the format of the Memory Control Packets (MCP). 3.7.3 STM: DDR-SDRAM Timing Register This register defines timing parameters that work with all DDR SDRAMs in the memory subsystem.
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Configuration Registers Device: NodeID Function: 1 Offset: C0h (Continued) Bit Attr Default Description TWR: Write to Read Delay 17:16 RW 1h The minimum delay from the Write command to the next Read command on the same branch DDR channel.This parameter is varied to avoid data strobe protocol violations on the DIMM data bus. Table 3-5 defines the settings of this parameter as a function of DMH parameters.
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Configuration Registers Device: NodeID Function: 1 Offset: C0h (Continued) Bit Attr Default Description TWA: Write to Activate Delay 5:4 RW 2h The minimum delay from the Read command to the next ACT command to the same bank. This parameter is programmed according to the DIMM timing parameters: tWR + tRP + 30ns Refer to DDR AC Characteristics specification for the timing parameters in the calculations.
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Configuration Registers A value of 0 indicates that refreshes should not be generated. For more information on refresh see Section 5.3.4, “DDR Maintenance Operations.” Device: NodeID Function: 1 Offset: 46h Bit Attr Default 15:12 RV 0 11:0 RW 0 Description Reserved Refresh Value 3.7.5 For DDR, the number of cycles between refreshes. For testing purposes, this field may be set from 0 to 50.
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Configuration Registers Device: NodeID Function: 1 Offset: 54h (Continued) Bit 28:26 Attr RV Default 0 Description Reserved IIO: Initiate Initialization Operation When set to 1, the execution of the initialization operation specified by the IOP starts. After the execution is completed, the SNC clears this bit to 0. The software must check to see if this bit is 0 before writing to this bit.
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Configuration Registers Table 3-6. DDR IOP Decodes Operation Name 3.7.7 Details DMH Register Read The serial read of the DMH register specified by the MRA field. The data read will be available in RCD register when IIO bit is cleared by hardware to 0. DMH Register Write The serial write of the DMH register specified by the MRA field. The write data is provided in the RCD register. DMH SIO Reset A SIO pin initialization sequence is sent to the DMH.
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Configuration Registers Device: NodeID Function: 1 Offset: 58h (Continued) Bit Attr Default Description Go Used only in test mode. 28 RW When set, initiates the test. When the test is complete, the SNC will reset this bit. This bit can therefore be polled to determine when the test is complete. Writing a 1 to this bit while it is already set will have no effect. Writing a 0 to this bit will have no effect. 0 Reduce Test Range This field is used for validation. It must be set to 000 in scrub mode.
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Configuration Registers 3.8 Reset, Boot and Control Registers 3.8.1 SYRE: System Reset This register controls SNC reset behavior. Any resets produced by a write to this register must be delayed until the configuration write is completed on the initiating interface (SP, processor bus, SMBus, JTAG).
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Configuration Registers This register is sticky through reset; that is, the contents of the register remain unchanged during and following a Hard Reset. This allows system configuration software to modify the default values and reset the system to pass those values to all host bus devices. The default values shown above represent the state of the register following a power-good reset. The CVDR bits do not affect SNC operation except for driving A[31:3]#.
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Configuration Registers Device: NodeID Function: 0 Offset: 44h (Continued) Bit 3.8.3 Attr Default Description 5:4 RWS 0 /RV Drive A[5:4]# 3 RWS 0 /RV Drive A[3]# 2:0 RV The use of these address bits during reset is reserved by the processor. The use of these address bits during reset is reserved by the processor. Drive A[34:32]# 0 The use of these address bits during reset is reserved by the processor.
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Configuration Registers Device: NodeID Function: 0 Offset: 48h (Continued) Bit Attr Default 9 RO 0 8 RO 0 7 RO 0 Description Enable BERR# Input Captured from A[9]#. If set, the SNC will enable BERR# reporting. A[8]# Value Captured from A[8]#. The use of these address bits during reset is reserved. In-order Queue Depth 1 Captured from A[7]#. If set, the SNC will limit its In-Order Queue Depth to 1, instead of the usual 8. 1 MEG Power-on Reset Vector 3.8.
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Configuration Registers 3.8.6 BOFL: Boot Flag This register is used to select boot strap CPU. The first time this register is read, it will return a non-zero signature. All reads thereafter will return 0s. This register can be re-initialized to the default value by the Boot Flag Reset bit in the SYRE register.This register is also memory mapped. See Section 3.2, “SNC Fixed Memory Mapped Registers.” Device: NodeID Function: 0 Offset: 74h Bit 3.8.
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Configuration Registers Device: NodeID Function: 2 Offset: 74h(31:0), 78h(63:32),7Ch(71:64) (Continued) Bit Attr Default 44:40 RO 11111 39:32 RO FFh 31:16 RV 0 Description SP1 Node ID [4:0] Device # received from SP1’s idle flits. SP1 Bus [7:0] Bus # received from SP1’s idle flits. Reserved StopOnErr 0 - An agent will send idle or info flits when in RETRY_LOCAL_IDLE state.
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Configuration Registers 3.8.9 FSBC: Processor Bus Control Register Device: NodeID Function: 0 Offset: 6Ch Bit Attr Default Description BERRINDIS: BERRIN# Disable 15 RW 0 If 0, SNC drives BERR# when BERRIN# is driven. If 1, SNC never drives BERR#. 14:11 RV 0 Reserved SST: Anti-Starvation Service Entry Threshold 10 RW 0 = The “service entry threshold” is 1. The first retry issued by the SNC while in normal mode will be considered the “first retry” for service.
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Configuration Registers Device: NodeID Function: 0 Offset: 70h (Continued) Bit 3.8.11 Attr Default 15:12 RW 0 11:8 RW 0 7:4 RW 0 3:0 RW 0 Description IDSEL for D8 Range IDSEL for the local firmware address range FFD8_0000h - FFDF_FFFFh. IDSEL for D0 Range IDSEL for the local firmware address range FFD0_0000h - FFD7_FFFFh. IDSEL for C8 Range IDSEL for the local firmware address range FFC8_0000h - FFCF_FFFFh.
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Configuration Registers Table 3-7. Enabling the LPC/FWH Interface 3.8.12 LPCEN Pin SNCINCO Bit[0]: LPCENPIN SNCINCO Bit[1]: LPCDIS 0 1 1 0 1 0 1 0 1 Tri-state all LPC outputs and mask all inputs. All LPC traffic (accesses to BIOS/PAL/SAL and FWH feature space) are routed to the SP. 1 0 0 LPC/FWH is enabled. LPC SP0INCO, SP1INCO: SP Interface Control These registers are common across all E8870 chipset components, and they provide the control and status for each SP.
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Configuration Registers Device: NodeID Function:2 for SP0INCO, 3 for SP1INCO Offset: C0h (Continued) Bit Attr Default Description Response Credits 18:16 RWS 101 15:13 RWS 101 12 RW Credits supported by this SP port on the response VC. Credit = 2size except that when size >= 101, credit = 25 instead of 32. These bits are sent in the idle flits. Must be set to a value <= to 25 for reliable SP operation. Request Credits Credit supported by this SP port on request VC.
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Configuration Registers 3.9 Error Registers 3.9.1 ERRCOM: Error Command This register enables error checking and flagging on various error conditions. Device: NodeID Function: 2 Offset: A4h Bit Attr Default Description 31:9 RV 0 Reserved 8:4 RV 11111 Reserved 3 RV 0 Reserved 2 RW 0 FTLFRZ: Error Freeze on Fatal Error 0 = Normal operation. 1 = Disable processor and SP interfaces when a Fatal error is observed or signaled on the error pins.
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Configuration Registers Device: NodeID Function: 2 Offset: 80h(31:0), 84h(63:32), 88h(96:64) Bit Attr Default ERR Type Description Last ERR[2]# Value If set, the ERR[2]# was asserted for four cycles before the SNC drives ERR[2]# for the first fatal error. This implies that some other component drove ERR[2]# first. 95 ROS 0 N/A If this bit is clear, but set in all other components, this component drove ERR#[2] first. When all fatal bits are cleared in this register, ERR[2]# sampling is reenabled.
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Configuration Registers Device: NodeID Function: 2 Offset: 80h(31:0), 84h(63:32), 88h(96:64) (Continued) Bit Attr Default ERR Type Description Processor Bus Errors (Continued) 85 RCS 0 Unc F8:BERR# Observed Set when the signal is asserted but not driven by the SNC. F9:Partial Merge Multi-Bit ECC error on IWB 84 RCS 0 Unc 83 RCS 0 Corr 82 RV 0 Corr 81 RCS 0 Corr A multi-bit error was detected when merging a partial memory write with the rest of the line supplied by IWB.
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Configuration Registers Device: NodeID Function: 2 Offset: 80h(31:0), 84h(63:32), 88h(96:64) (Continued) Bit Attr Default ERR Type Description Memory Errors (Continued) M3: Uncorrectable Memory ECC Error on Memory Scrub 37 RCS 0 Unc The SNC has poisoned the Memory ECC codeword that contained the error and written the data back to memory. See Section 5.2, “Error Correction.
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Configuration Registers Device: NodeID Function: 2 Offset: 80h(31:0), 84h(63:32), 88h(96:64) (Continued) Bit Attr Default ERR Type Description Scalability Port Physical Layer Errors (Continued) S2: SP Multi-Bit Data ECC Error 19 RCS 0 Unc An uncorrectable ECC error was detected in data on an incoming flit. The uncorrected data will be passed to the processor bus, memory interface or configuration space. Section 6.1.1, “End-to-end Error Correction” describes the action taken at these interfaces.
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Configuration Registers Device: NodeID Function: 2 Offset: 80h(31:0), 84h(63:32), 88h(96:64) (Continued) Bit Attr ERR Type Default Description Configuration Access Errors C1: Multi-Bit Data ECC Error on Configuration Write 3.9.3 1 RCS 0 Fatal 0 RCS 0 Corr The SNC will complete the configuration write on all interfaces, but not perform the register write. C2: Single-Bit Data ECC Error on Configuration Write The SNC will correct the error and perform the register write.
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Configuration Registers Device: NodeID Function: 2 Offset:98h(31:0), 9Ch(63:32), A0h(71:64) (Continued) Bit 3.9.5 Attr Default Description 77:40 RV 0 Reserved 39:32 RW 1 0 = no effect. 1 = mask the corresponding bit in FERRST and SERRST. 31:21 RV 0 Reserved 20:16 RW 1 0 = no effect. 1 = mask the corresponding bit in FERRST and SERRST. 15:10 RV 0 Reserved 9:0 RW 1 0 = no effect. 1 = mask the corresponding bit in FERRST and SERRST.
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Configuration Registers Device: NodeID Function: 0 Offset: CCh(31:0), D0h(63:32), D4h(95:64) (Continued) Bit 50:41 Attr Default ROS 0 Description Defer ID. A[43:3]: 40:0 3.9.6 RWS/ ROS 0 This field is used for address logging and is not writable. For non-coherent and I/O write transactions on the SP, this address is the same as the one in the SP request packet. A[6:3]#, A[5:3]#, A[4:3]#, or A[3]# may be zeroed to satisfy burst ordering requirements.
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Configuration Registers Device: NodeID Function: 0 Offset: DCh(31:0), E0h(63:32), E4h(95:64) (Continued) Bit 50:41 Attr Default ROS 0 Description DID[9:0]. A[43:3]: 40:0 3.9.7 RWS/ ROS This field is used for address logging and is not writable. For non-coherent and I/O write transactions on the SP, this address is the same as the one in the SP request packet. A[6:3]#, A[5:3]#, A[4:3]#, or A[3]# may be zeroed to satisfy burst ordering requirements.
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Configuration Registers Device: NodeID Function: 2 Offset: 50h(31:0), 54h(63:32),58h(71:64) Bit 3.9.10 Attr Default Description 71:64 ROS 0 DEP[7:0] 63:0 ROS 0 D[63:0] Data in error. This could be the upper half or the lower half of the data bus. REDSPL[1:0]: SP Non-fatal Error Data Log This register latches Syndrome and ECC information for the first ECC error detected on incoming SP data. See Section 6.5, “Chipset Error Record” for a listing of the errors that use this log.
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Configuration Registers 3.9.12 RECMEM: Recoverable Error Control Information of Memory This register latches control information for the first non-fatal memory error detected by the SNC. The address of the error can be inferred from the MIR and MIT register settings. The contents of this register is only valid when one of the errors that set this register is logged in the FERRST register.
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Configuration Registers Device: NodeID Function: 1 Offset:D4h(31:0), D8h(63:32), DCh(95:66) (Continued) Bit Attr Default Description Syndrome 63:32 ROS 0 The bit in error can be calculated from this field and the Locator field. Section 5.2.4, “Memory Error Correction Code” describes the H matrix used for this calculation. Locator The Server ECC Locator which identifies the symbol in error for correctable errors. Exactly one bit should be set if the error is correctable.
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Configuration Registers Device: NodeID Function: 3 Offset: 50h Bit 15:10 Attr Default RV 0 Description Reserved SPPM Count Status The OR of both Event Status bits reported by either SPPM module for an overflow or max comparison condition, i.e., SPPMR[0].EventStatus[0] OR 9 RO 0 SPPMR[0].EventStatus[1] OR SPPMR[1].EventStatus[0] OR SPPMR[1].EventStatus[1] The status condition can be cleared by writing zeros to the Event Status field of the affected PMR register.
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Configuration Registers Device: NodeID Function: 3 Offset: 50h (Continued) Bit Attr Default Description Local Count Enable 1 RW Setting this bit to a ’1’ will enable any counter on this component which has “local count enable” assigned as the enable source in the CE_Src field of its individual PMR register. Writing a ’0’ to this bit will disable the counters. 0 Note: When using the Interval Timer this field must be set to ’0’.
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Configuration Registers Device: NodeID Function: 3 Offset: 52h (Continued) Bit Attr Default Description Timer Prescale This field determines the rate at which the timer will count in terms of the SNC internal clock. 10:8 RW 0 000 001 010 011 100 101 110 111 1x 2x 4x 8x 16x 32x 64x 128x Repetitive Mode 7 RW 0 Setting this bit to ’1’ enables the interval timer repetitive mode.
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Configuration Registers 3.10.3 PMINIT: Timer Initial Value Register The contents of this register is preloaded into the Interval Timer at the start of each sample period. A sample period is initiated by setting the Timer Enable bit in the PTCTL register or is automatically re-initiated in the repetitive mode after the completion of each sample interval. Device: NodeID Function: 3 Offset: 54h Bit Attr Default Description Initial value of the Countdown Timer 31:0 3.10.
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Configuration Registers Note: For these first two methods, bit 31 of the PMC should typically be set to 0. The comparison does include bit 31 (overflow) of the PMD counter, but since the overflow sets the counter status, a subsequent comparison will not affect the status condition. The third mode is an address comparison mode. PMD0 compares on addresses greater than the PMC0 register and PMD1 compares on addresses less than or equal to PMC1.
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Configuration Registers Device: NodeID Function: 3 Offset: A0h (FSBPMR0), E0h(FSBPMR1) (Continued) Bit Attr Default Description Compare Mode This field defines how the PMC (compare) register is to be used. 00 - Compare mode disabled (PMC register not used) 01 - Max compare only: The PMC register value is compared with the counter value. If the counter value is greater, the Count Compare Status (bit 13) of the “Event Status” field of this register will be set.
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Configuration Registers Device: NodeID Function: 3 Offset: A0h (FSBPMR0), E0h(FSBPMR1) (Continued) Bit Attr Default Description Count Mode 00 - Count event selected by Count Event Select field. 01 - Count clocks after event selected by Count Event Select field. 15:14 RW 0 10 - Count transaction length, in quad words, of event defined by the Bus Events PME registers (FSBPMEL and FSBPMEH.) Note: The Count Event field and Event Group Selection fields should select the Bus Events PME registers.
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Configuration Registers Device: NodeID Function: 3 Offset: A0h (FSBPMR0), E0h(FSBPMR1) (Continued) Bit Attr Default Description Clear Overflow 1 RW 0 This bit clears overflow bit in associated PMD counter. The counters continues counting. This bit is cleared by hardware when the operation is complete. Reset 0 RW 0 Setting this bit resets all registers associated with this counter to the default state.
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Configuration Registers Device: NodeID Function: 3 Offset: ACh (FSBPMEL0), ECh(FSBPMEL1) (Continued) Bit Attr Default Description Request Type (AND’ed Group) 17:5 RW 1xxxxxxxxxxxxDeferred Phase (OR’ed with other group qualifications, not AND’ed) x1xxxxxxxxxxxDeferred Replies (Address range must be programmed inactive) xx1xxxxxxxxxxInterrupt Acknowledge xxx1xxxxxxxxxSpecial Cycles xxxx1xxxxxxxxCache Line Replacement xxxxx1xxxxxxxMemory Read Current xxxxxx1xxxxxxI/O Reads xxxxxxx1xxxxxI/O Writes xxxxxx
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Configuration Registers Device: NodeID Function: 3 Offset: B0h (FSBPMEH0), F0h(FSBPMEH1) (Continued) Bit Attr Default Description Agent IDs (AND’ed Group) 8:4 RW 1xxxx x1xxx xx1xx xxx1x xxxx1 0 SNC CPU/Package 3 CPU/Package 2 CPU/Package 1 CPU/Package 0 Extended Functions (AND’ed Group) Note: “0000” will match anything. 3:0 3.10.10 RW 1xxx x1xx xx1x xxx1 0 EXF4 EXF3 EXF2 EXF1 FSBPMER[1:0]: Processor Bus Performance Monitor Resource Events This register is used to select resource events.
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Configuration Registers Device: NodeID Function: 3 Offset: B4h (FSBPMER0), F4h(FSBPMER1) (Continued) Bit Attr Default Description Queue Events This field selects a queue to monitor and which event measurement to make for that queue. The “no measurement” selection should be selected to disable this measurement.
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Configuration Registers Device: NodeID Function: 3 Offset: B8h (FSBPMEU0), F8h (FSBPMEU1) (Continued) Bit Attr Default Description Threshold Comparison 19:13 RW 0 12 RW 0 11 RW 0 10 RW 0 9 RW 0 8 RW 0 7 RW 0 6 RW 0 5 RW 0 4 RW 0 3 RW 0 2 RW 0 Value compared against number of entries in the selected queue of buffer. Clocks are counted (utilization), if the number of entries in the queue are greater than the value in the Threshold Comparison field.
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Configuration Registers 3.10.12 SPPMD[1:0]: SP Performance Monitor Data This is the performance monitor counter. The overflow bit can be cleared via the PMR register without perturbing the value of the counter. This counter is reset at the beginning of a sample period unless preloaded since a prior sample. Therefore, the counter can be preloaded to cause an early overflow, otherwise it will be reset at the start of a sample period. Device: NodeID Function: 2 Offset: E8h (SPPMD0), F8h (SPPMD1) Bit 3.10.
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Configuration Registers 3.10.14 SPPMR[1:0]: SP Performance Monitor Response The PMR register controls operation of its associated counter, and provides overflow or max compare status information. Device: NodeID Function: 2 Offset: E0h (SPPMR0), F0h(SPPPMR1) Bit Attr Default Description 31:26 RV 0 Reserved 25 RW 0 0 = Request Bus 1 = Response Bus 24 RW 0 This bit has no effect on SNC operation.
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Configuration Registers Device: NodeID Function: 2 Offset: E0h (SPPMR0), F0h(SPPPMR1) (Continued) Bit Attr Default Description Count Event Select This field determines the counter enable source. 18:16 RW 000 001 010 011 100 101 110 111 0 PME register event Partner event status (max compare or overflow) All clocks when enabled Reserved EV0 pin EV1 pin EV2 pin EV3 pin Count Mode 00 = count event selected by Count Event Select field.
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Configuration Registers Device: NodeID Function: 2 Offset: E0h (SPPMR0), F0h(SPPPMR1) (Continued) Bit Attr Default Description CE_Src: Counter Enable Source These bits identify which input enables the counter. Default value disables counting.
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Configuration Registers Device: NodeID Function: 2 Offset: ECh (SPPMD0), FCh(SPPMD1) (Continued) Bit Attr Default Description Packet Src Node 20:16 RW 0 15:14 RW 0 1111 xxxxx All sources Src Node ID (except 11111) SP Port Select x1 - SP0 1x - SP1 Packet Type Selection Group Type Data XXXXYYC 13:7 RW For request packets, the fields are: [13:10] - XXXX is the request type major encoding [9:8] - YY is the request type minor encoding [7] - C is the coherency bit For response packets, the fields
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Configuration Registers Device: NodeID Function: 3 Offset: 60h (Continued) Bit Attr Default Description Resolution Determines the address range for each counter 17:15 RW 0 000 001 010 011 100 64-bytes 4 KB 128 KB 8 MB 256 MB Filter Select (Conditioned Addresses) 14 RW 0 0 = All transaction types. The retried transactions are also counted. To filter retried transactions, set this bit and use the FSBPME0 “completion status” field to eliminate retried cycles.
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Configuration Registers 3.10.17 HPADDR: Hot Page Index This register is used in conjunction with the HPDATA register to access the Hot Page Counter Array. It contains the index used to access the array. If the most significant bit is set, the index is automatically incremented after each access to the HPDATA register. The size of the Hot Page counter array is 2KB. Device: NodeID Function: 3 Offset: 64h Bit Attr Default Description Array Index Auto-increment 3.10.
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Configuration Registers 3.10.20 HPBASE: Hot Page Range Base This register contains the base address used to index the Hot Page counter array. A 2K-entry counter array can scan up to 512 GB of contiguous physical addresses when the address resolution is 256 MB. Device: NodeID Function: 3 Offset: 70h Bit 31:27 Attr RV Default 0 Description Reserved Base Address of the Counter Array Corresponds to A[43:17]#. The least significant bits are ignored dependent on the resolution: 26:0 3.10.
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Configuration Registers 3.10.22 HPRCTR: Hot Page Range Counter This register contains the value of the Range counter which is used in the AutoRange mode. This counter is initially loaded with the Hot Page Base (HPBASE) register. After each sample interval, defined by the interval timer, the Range Counter is incremented to the next range of 512 address blocks.
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Configuration Registers 3-66 Intel® E8870 Scalable Node Controller (SNC) Datasheet
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4 System Address Map 4.1 Memory Map The Itanium 2 processor provides address bits for a 50-bit address space. The SNC support 44 bits of addressing 1. The E8870 chipset treats accesses to several address ranges in different ways. There are fixed ranges like the compatibility region below 1 MB, interrupt delivery range, and the system region located in the 32 MB directly below 4 GB. In addition, there is a variable region for memorymapped I/O.
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System Address Map 4.1.1 Compatibility Region This is the range from 0 to 1 MB (0_0000h to F_FFFFh). Requests to the compatibility region are directed to main memory, the compatibility bus, or the VGA device. Physical DRAM addressed by requests in this region that are mapped to the compatibility bus is not recovered. This region is divided into four ranges. Regions below 1MB that are mapped to memory are accessible by the processors and by any PCI bus. Note: 4.1.1.
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System Address Map The default for these segments at power-on is that they are mapped read/write to the compatibility bus. Software should not set cacheable memory attributes for any of these ranges unless both reads and writes are mapped to main memory. In the write protect case, the E8870 chipset cannot guarantee write protection if an Implicit write-back occurs. This will result in a write-back to memory. If a Bus Read Invalidate Line or explicit write-back is issued, the E8870 chipset will malfunction.
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System Address Map Some FWH components implement more than 4 MB of firmware space. These components support internal paging registers to allow software to map the SNC 4MB window into the larger component. In other words, software will first program the paging register to move the base address and subsequent accesses to the firmware will be offset by that amount. Only single-byte writes are supported to this range. These writes are interpreted as commands by the Flash device.
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System Address Map Figure 4-2. Firmware Map Example using Intel® E8870 Chipset and Intel 82802 FWH with Local Firmware Enabled Processor System Bus Address Register for IDSELs FWH A22 FFF8_0000h - FFFF_FFFFh SNC.FWHSEL: F8 Range FFF0_0000h - FFF7_FFFFh SNC.FWHSEL: F0 Range FFE8_0000h - FFEF_FFFFh FFE0_0000h - FFE7_FFFFh FFD8_0000h - FFDF_FFFFh Local Firmware Range (4 MB) FFD0_0000h - FFD7_FFFFh FSBC. FEATEN North BIOS or North Register Space (Depends on FEATEN Field in FSBC Register) SNC.
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System Address Map Figure 4-3. Firmware Map Example using Intel® E8870 Chipset and Intel 82802 FWH with Local Firmware Disabled Processor System Bus Address Register for IDSELs A22 FFF8_0000h - FFFF_FFFFh ICH4.FWHBIOS: F8 FFF0_0000h - FFF7_FFFFh ICH4.FWHBIOS: F0 FFE8_0000h - FFEF_FFFFh ICH4.FWHBIOS: E8 FFE0_0000h - FFE7_FFFFh ICH4.FWHBIOS: E0 1 Upper South BIOS FFD8_0000h - FFDF_FFFFh ICH4.FWHBIOS: D8 FFD0_0000h - FFD7_FFFFh ICH4.FWHBIOS: D0 FFC8_0000h - FFCF_FFFFh ICH4.
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System Address Map 4.1.2.4 Chipset Specific Range The address range FE00_0000h - FFBF_FFFFh region is reserved for chipset specific functions. FE60_0000h - FE6F_FFFFh is used for memory mapped SNC registers. They are accessible only from the processor bus on that SNC. The E8870 chipset will master abort requests to the remainder of this region. 4.1.3 High and Low Memory Mapped I/O (MMIO) Two variable-sized MMIO regions are directed to I/O buses.
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System Address Map Interface subrange is routed there. An SP request that falls in the MMIO range, but is not mapped to any Hub Interface in that SIOH will be master aborted. 4.1.4 Memory Mapped Configuration Space The entire PCI configuration space is mapped into the MMCFG address range of the SNC. The processor bus address defines the configuration register to be accessed and the processor bus data either returns or provides register contents.
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System Address Map memory is generally global. Multiple processor bus systems use local memory while booting, however. Local memory can be defined during system operation in multiple processor bus systems, but this possibility is not validated for E8870 chipset-based systems. 4.1.5.3 Routing Memory Requests Initiated on a Hub Interface When a request appears on a Hub Interface, and it does not fall in any special region, the request is directed to the scalability port (SP) with Attr = DRAM.
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System Address Map 4.1.5.3.5 128-byte Interleave Example Figure 4-4 describes the 128-byte interleaving of 16 GB of memory in a single-domain system with various amounts of memory and different technologies on each node. The SPS MIRs define global interleave ranges. An address range and the nodes assigned to each of the four ways is associated with each SPS MIR. SNC MIRs define local interleaves.
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System Address Map Global interleave range 2 extends from 10 to 12 GB. It consists of two 1-GB blocks interleaved across SNCs 0 and 1. Even ways 00 and 10 belong to SNC0. Odd ways 01 and 11 belong to SNC1. Global interleave range 3 extends from 12 to 13 GB. It consists of two 500-MB blocks interleaved across SNCs 0 and 1. SNC0 MIR[3] defines a local interleave that spans multiple global interleaves. This is possible whenever a single technology can occupy the same way in consecutive global interleaves.
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System Address Map To avoid memory scrubbing problems, reflection size must be 4 GB maximum. The highest address of the reflection is restricted to end on a 4-GB boundary. Both the highest address in the MIR and the reflection of address FFFF_FFFFh must appear just below a 4-GB boundary (Nx4GB - 1). This ensures that the address bits A[31:0]# are the same for the reflection of an address and the original. The physical memory mapped by MIR1 to 2 to 4 GB can also be mapped to 6 to 8 GB by MIR2.
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System Address Map Table 4-3. SPS Memory Mapping Registers Name 4.2.1.3 Function MIR[5:0] Defines the home node for each cache line of main memory. MMIOLS Splits the low MMIO range into subranges that are routed to different SIOHs. MMIOHS Splits the high MMIO range into subranges that are routed to different SIOHs. VGA_PORT Defines the port number of the SIOH that holds the VGA bus. CB_PORT Defines the port number of the SIOH that holds the compatibility bus.
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System Address Map Any other encodings are treated as DND. That is, they are not used for routing. The Attr field is not used in the routing of coherent requests. The following tables define the address disposition for the E8870 chipset. Table 4-6 defines the disposition of outbound requests entering the SNC on the processor bus. Table 4-8 defines the disposition of inbound requests entering the SIOH on hublinks. Table 4-6.
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System Address Map Table 4-6. Address Disposition for Processor (Continued) Address Range Conditions MMIOL.BASE b Low MMIO Above FDFF_FFFFh. E8870 Chipset Specific to SNC Behavior SPS Behavior Issue non-coherent Read/ Write to SP, Attr = MMIO Route to SIOH according to MMIOLS. FE00_0000h to FEBF_FFFFh AND valid SNC memory mapped register address Issue configuration access to memory mapped register inside SNC. N/A FE00_0000h to FEBF_FFFFh AND NOT a valid SNC memory mapped register address.
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System Address Map Table 4-7. Intel® E8870 Chipset SAPIC Interrupt Message Routing and Delivery Source SIOH SNC, NodeId = A[19:15]# SNC, NodeId != A[19:15]# Type Routing Physical Directed Delivered to SNC with NodeId = A[8:4]#. Message is presented directly on processor bus. Physical Redirectable Delivered to SNC with NodeId = A[8:4]#. Redirection is performed by the SNC. Physical Directed SNC completes transaction.
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System Address Map Table 4-8. Address Disposition for Inbound Transactions (Continued) Address Range Inbound Writes Inbound Reads SIOH Behavior for Inbound SPS Behavior 0B_0000h to 0B_7FFFh and (MDA_en = 0) and (VGA_port = none) DRAM DRAM Route to SPS, Attr=DRAM. Route to SNC according to MIR registers. Apply Coherence Protocol. 0C_0000h to 0F_FFFFh DRAM DRAM Issue Coherent Request to SP. Route to SNC according to MIR registers. Apply Coherence Protocol.
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System Address Map 4.2.3 Local/Remote Decoding for Requests to Main Memory The SNC treats all accesses to main memory as coherent. For main memory accesses, the address is compared against the local1 MIR registers to determine whether it accesses local memory or memory on a different node. Generally, for local accesses, the SP request is just a snoop, and any memory access is performed by the memory controller. For remote memory accesses, the SP request will include a read or write to the home node.
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System Address Map 4.3.2 Outbound I/O Access The E8870 chipset allows I/O addresses to be mapped to resources supported on the I/O buses underneath the E8870 chipset controller. This I/O space is partitioned into 32 2KB segments. Each of the I/O buses can have from 0 to 32 segments mapped to it. Each PCI bus gets contiguous blocks. All PCI buses on a given SIOH must be assigned contiguous blocks. The lowest block, from 0 to 0FFFh, is always sent to the compatibility bus. Figure 4-6.
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System Address Map starting at 53BCh includes 53BC-53BFh. Since A[9:0] = 3BFh for 53BFh, it should be routed to CB. 2. I/O Addresses Used for VGA Controllers: If the VGASE bit in the ASE register is set, and each addressed byte is in the following range (A[15:10] are ignored for this decode): A[9:0] = 3B0h-3BBh, 3C0h-3DFh, an I/O Read/Write will be sent out the default SP with Attr=VGA. For example, a 2-byte read starting at 23BBh includes 23BB-23BCh.
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System Address Map The E8870 chipset provides memory mapped configuration mechanisms. See Section 4.1.4, “Memory Mapped Configuration Space” and Section 4.1.2.4, “Chipset Specific Range.” 4.5 Illegal Addresses 4.5.1 Master Abort The term “master abort” is used in E8870 chipset specifications as shorthand for “Reads return all 1’s. Writes have no effect.” The SNC will master abort processor transactions by one of the following methods: • Re-directing them to the compatibility bus.
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System Address Map 4-22 Intel® E8870 Scalable Node Controller (SNC) Datasheet
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5 Memory Subsystem The memory subsystem consists of: • Memory controller and data buffers • DDR-SDRAM memory hub interface component (DMH) and DDR DIMMs Table 5-1. General Memory Characteristics Item Description DRAM Types DDR-SDRAM Memory Modules 72-bit DDR-SDRAM DIMMs DRAM Technologies 128, 256, 512 Mb and 1 Gba densities Speed Grades DDR: Tcas = 1.5, 2.0, 2.5. Trcd = 20, 30, 40 ns Peak Bandwidth 6.
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Memory Subsystem 5.1.2 Reads 5.1.2.1 Read Decoding The request is decoded for interleave range, then for targeted memory resources (channel, device/ DIMM row, DRAM row, DRAM column) and destination. If a read does not fall in a range covered by the SNC MIRs (a “MIR miss”, see Section 3.6.9, “MIR[9:0]: Memory Interleave Range Registers”), the memory controller will drop the request. A MIR miss on a processor request means the addressed memory is in another SNC, or the access was a programming error.
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Memory Subsystem Table 5-2. Indices to Re-Ordering Queues DDR Index All Cases 1 Bank[0] is selected. 0 If all bits of MIR.WAY are set, Bank[1] is selected; If not, Channel[0] is selected. 5.1.3 Writes 5.1.3.1 Write Decoding Writes are decoded for interleave range, then for targeted memory resources (channel, device/ SDRAM row, DRAM row, DRAM column) and destination. If the write is not in any range described by the MIRs on that SNC (a “MIR miss”, see Section 3.6.
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Memory Subsystem If this bit is set, the SNC will accumulate writes before bursting them: • Whenever no reads are ready to be issued, and a sufficient interval has elapsed since the last read to allow a write to be issued immediately, and there are four writes to flush, at least four writes will be issued. This burst will continue until all writes are completed or a read is accepted by the memory controller. According to this policy, up to three writes can be posted indefinitely in the SNC. MC.
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Memory Subsystem The operating system guarantees that only one of these addresses will be generated by a processor. No conflict will be detected between a processor write to the legitimate address and a scrub write to the alias. Therefore, the scrub engine must not generate writes to the aliases. Use of reflections are limited to recovering memory behind MMIOL to allow scrub hardware to identify these aliases. Then there are only two cases of aliases, addresses in the range MMIOL.
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Memory Subsystem Figure 5-1.
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Memory Subsystem Figure 5-2.
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Memory Subsystem The 18 main channel data bits cannot be evenly divided among the eight devices providing the packet (this is why there are some 12-bit symbols and some 8-bit). Therefore, IDM defines a rotating series of eight addresses over which each device drives each symbol. Since the main channel request lines are duplicated for each of the four main channels, an address error outside the SNC is highly likely to be detected prior to use.
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Memory Subsystem All addresses mapped by the MIR will be tested whether they fall in ranges mapped to main memory or not. For example, addresses will still be tested where the MIR overlaps MMIOL. Prior to test, the first 32 lines in the MIR must be written with a test pattern. Setting the MTS MTS.GO bit causes the test pattern to be duplicated throughout the range. The memory controller must be able to service processor requests to addresses outside the test range while memory test is running.
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Memory Subsystem Figure 5-3. Typical DDR-SDRAM Memory System Processor Bus DDR DIMMs RD[17:0] DDR DIMMs DMH SNC DDR DIMMs RD[35:18] DDR DIMMs DMH DDR DIMMs RD[53:36] DDR DIMMs DMH DDR DIMMs DDR DIMMs RD[71:54] DMH 5.3.1.2 Configuration for Performance For best performance, the amount of memory on each DMH DDR channel should be the same. Table 5-3.
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Memory Subsystem The DMH will compare read addresses to the posted writes and substitute queued data for DIMM data with the same timing as a DIMM read. The SNC delays read and write issue on the main channels to avoid timing conflicts on the DDR data bus and in the DRAMs. Since the write issued on main channel causes a write to a different address on the DDR bus, the SNC must use the DDR address for timing conflict checks. 5.3.2.2 DDR Reordering Policies See Section 5.1.2.
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Memory Subsystem The minimum configuration is 512 MB: 1 DIMM (total of 128MB) device on each DMH. The maximum configuration is 128 GB: 8 DIMMs (total of 32GB) devices on each DMH. Table 5-4. Bits Used in MCP Packet for Different DDR Technologies Technology 128 Mb 256 Mb 512 Mb 1 Gba a.
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Memory Subsystem provide the critical word in the early half of the main channel data packet. However, the SNC does not perform this optimization. All main channel data packets have the same data bit mapping. The SNC always sets CA[10] to indicate auto-precharge, and it is never mapped to any address bit. Interleave Field Table 5-6 shows how low-order address bits are mapped to any DDR Channels, DIMM sides and DRAM Banks that are included in an interleave.
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Memory Subsystem High-order Field Bits that are required to address a given technology (the number of rows, columns or channels specified by the MIT register), but do not appear in the fixed or interleave fields, appear in the high-order range. These bits are assigned to address bits as defined in Table 5-5. Note: CA[10] does not appear in this field, since DDR uses this for an auto-precharge indication. No bit in the high-order field is mapped to an address bit under all conditions.
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Memory Subsystem 5.3.4 DDR Maintenance Operations The maintenance operations that may occur are DIMM Refresh, DMH Current Calibration, DMH Temperature Calibration, SNC RAC Temperature Calibration, and SNC RAC Current Calibration. The current and temperature calibration period (100 ms) is long enough that there is not a significant performance impact. DDR refreshes are issued for all 16 possible Device Rows every 15.6 us. Refreshes are issued whether the DIMMs are populated or not.
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Memory Subsystem 5-16 Intel® E8870 Scalable Node Controller (SNC) Datasheet
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Reliability, Availability, and Serviceability 6 This section describes the features provided by the E8870 chipset that play a role in the design and development of high Reliability, Availability and Serviceability (RAS) systems. This chapter describes the E8870 chipset support for system integrity. The E8870 chipset provides error logging and employs a method called end-to-end error detection for data errors. These features support identification of the first system error and its source.
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Reliability, Availability, and Serviceability Table 6-1. Intel® E8870 Chipset Errors ERR# Type Error Name Response Log Log Registers Processor Bus F1 Fatal Illegal or Unsupported Transactiona,b Hardfail, drop transaction.c Control NRECFSB F2 Fatal Bus Protocol Errord Hardfail. Control NRECFSB N/A N/A F3 Fatal BINIT# Observed SNC reset, memory maintained. F4 Fatal Processor Bus Address Parity Errorb Hardfail, drop transaction.
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Reliability, Availability, and Serviceability Table 6-1. Intel® E8870 Chipset Errors (Continued) ERR# Type Error Name Response Log Log Registers Memory (cont) M7 Corr Correctable Memory ECC Error on Read or Memory Scrub Reads: Correct returned data. Scrub: Correct error and write to memory. Control, syndrome. RECMEM, REDMEM M8 e Corr Partial Merge Single-Bit DATA ECC Errore Correct error and write to memory.
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Reliability, Availability, and Serviceability Table 6-1. Intel® E8870 Chipset Errors (Continued) ERR# Type Error Name Response Log Log Registers SP Protocol Layer (cont) P8 Corr Illegal SP Address Errorl Master abort. Request header. RECSPP RECSPPD(S PS) P10 Corr Received Master Abort Responsem Master abort. Response header. RECSPP RECSPPC(S PS) C1e Fatal Configuration Multi-Bit DATA ECC Error (write only) Register contents not updated; normal completion response.
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Reliability, Availability, and Serviceability e. f. g. h. i. j. k. l. m. n. o. p. 6.1.1 ECC checking, correction and/or poisoning is done within the 8B boundary of the partial write. FWH slave device indicates error or sync/response handshake in error. Address A[31:3] and transaction type only is logged. Set if no LPC/FWH device drives a valid SYNC after four consecutive clocks. Number of retries logged if LLR is successful.
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Reliability, Availability, and Serviceability 6.1.1.1 Exceptions • No checks will be done on FWH and configuration register read transactions. • Write to FWH will be checked at processor bus. Processor bus errors will be logged. Failing FWH write data will not be logged. 6.1.2 Data Poisoning Data covered by SEC/DED ECC is poisoned by flipping checkbits[7:1]. Memory write data, which is covered by chipset memory ECC, is poisoned by flipping symbol g on RAC1 and RAC3.
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Reliability, Availability, and Serviceability For reliable signaling of errors in the system, each component guarantees that the pin associated with the error is asserted within four system clock cycles (200 MHz) after the error is detected by the component. For example, if a multi-bit ECC error is detected at the SP interface in cycle x, the uncorrectable error pin (ERR[1]#) is asserted in cycle x+3. 6.1.
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Reliability, Availability, and Serviceability • If MDFC is enabled, uncorrectable ECC errors on a memory read will poison the SEC/DED ECC. For uncorrectable ECC errors detected on memory writes, the MFDC code is poisoned. • To correct single-bit errors in memory, the memory controller will “walk” the memory, reading, then writing each location. The interval between each “scrub” is 65536 cycles of 200 MHz clocks. Errors remain in memory until they are scrubbed. 6.1.4.
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Reliability, Availability, and Serviceability An entry times-out if the counter wraps around (toggles the high-order) bit twice. As a result, the time-out period can be from 1 x to 2 x the timer value. Using such a mechanism, it is possible for multiple entries in a queue to time-out simultaneously. When a time-out occurs, the hardware selects one entry as the “first error” for logging in the FERRST. The presence of more than one error is indicated in the SERRST register. 6.
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Reliability, Availability, and Serviceability 6.2.2 Server Management (SM) SM provides “out-of-band” error handling features for high RAS systems on the Itanium processor family: • Error logging. • Remote diagnostics. • Re-configuration (graceful degradation). In case of a catastrophic event, SM can analyze and isolate troublesome components and assist the system boot after a reset. 6.2.3 OS/System Software • Resume from correctable errors.
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Reliability, Availability, and Serviceability 6.2.5 Summary Table 6-2 summarizes the different roles played by different RAS components. RAS components must be designed to work closely with each other to provide good system RAS. Table 6-2. RAS Roles of Different System Components RAS Tasks Hardware MCA SM Device Driver OS/BIOS Error Logging 1 instance NVRAM NVRAM Report to OS Report to MCA. Error Containment Data poisoning, hardfail response, machine check via BERR#/MCERR#.
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Reliability, Availability, and Serviceability • Failed PCI slots. Failed PCI slots is isolated by PCI hot-plug hardware. • Failed P64H2. Failed P64H2 is isolated by disabling the Hub Interface 2.0 interface. • Failed ICH4. Failed ICH4 is isolated by disabling the Hub Interface 1.5 interface. 6.4 Hot-Plug Care must be taken on module partitioning to enable maximum RAS.
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Reliability, Availability, and Serviceability • The ability for system software to generate an interrupt through the SP, and software scratch bits provided per SP port. This allows system software to use one interrupt for hot-plug addition and removal sequencing. • Control and status is provided in a register provided per SP interface. On the SPS, this register is called the SPINCO register.
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Reliability, Availability, and Serviceability BusNum // Bus number on which component resides DevNum // Device number of the component, also known as E8870 NodeId FuncNum // Function ID DevID // PCI device ID (identifies the component) RevID // Device revision ConfigSpaceNumReg// Number of registers listed for this function Length // length of this function log in byte Table 6-3.
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Reliability, Availability, and Serviceability Table 6-3. Intel® E8870 Chipset Error Status and Log Registers (Continued) Component Function Reg_ID Register Name Size (Bytes) Description SIOH 0-4 5C REDHUB 12 Hub Interface data log for non-fatal errors. SIOH 0-4 68 NRECHUB 16 Hub Interface control log for fatal errors. SIOH 6 84 RECSPL0 8 SP0 Link layer control log for nonfatal errors. SIOH 6 8C REDSPL0 2 SP0 Link layer data log for non-fatal errors.
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Reliability, Availability, and Serviceability These errors do not compromise further chipset operation. These errors leave an error status and log trail as the error propagates from one component to its destination. There are three types of trailing errors detected by the chipset: 2x ECC, 1x ECC, and master abort. Each CT error can be an error source, midpoint, and/or endpoint. Table 6-4 provides general information for all of the errors detected by the E8870 chipset.
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Reliability, Availability, and Serviceability . Table 6-4.
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Reliability, Availability, and Serviceability Table 6-4.
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Reliability, Availability, and Serviceability Table 6-4.
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Reliability, Availability, and Serviceability 6.5.4 ESP Error Logs This section provides the format of the contents of the log registers for SP link layer and SP protocol layer errors. The contents of the error logs vary with the type of the error that is detected. Table 6-5 and Table 6-6 show the contents of the error log when the type of information that is logged for the error is “control” information. . Table 6-5.
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Reliability, Availability, and Serviceability Table 6-6. Control: SP Response Header Error Log (Continued) SP Response Header Fields Field Name XAddr Description Number of Bits in Header 6 X Address bits from request packet are returned in this field for routing of response Reserved 87 For future use Prot 16 Error protection Total Bits Error Log Field 32:27 144 37 For SP link layer ECC errors, information is logged in a data log register (REDSPL). Table 6-7 shows the contents of this log.
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Reliability, Availability, and Serviceability 6-22 Intel® E8870 Scalable Node Controller (SNC) Datasheet
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Clocking 7.1 7 System Clocking In systems employing the E8870 chipset, the phase of the clock routed to each component can be arbitrary, although the variation in phase (drift) must be controlled. All of the signals between the SNC, SPS, and SIOH are source synchronous, or function asynchronously, allowing greater flexibility in the distribution of the system level clocks. Agents that have common clock interfaces need clocks delivered in-phase.
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Clocking Clock Distribution Scheme CPU Node Connector n Processor n RAC Interface Clocks CTM / CFM to/from MRH-Ds x4 pairs 2 2 2 2 SYNCLK/N x4 33MHz 2 2 PCLK/M x4 DMCG FWH FWH DMCG CKMREF DMH DMH DMH DMH PCI Slot 0 P64H2 n 33/66/100/133MHz P64H2 P64H2 PCI Slot n 66MHz CKFF 66MHz PCI Clock Buffer 66MHz 66MHz 48MHz 48MHz 33MHz 66MHz FBCLK 14.3MHz Ext.
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Clocking Processor and chipset reference clock inputs are differential. Each chipset component has a pair of differential clock input pins, BUSCLK+ and BUSCLK- on the SNC components, and SYSCLK+ and SYSCLK- on the SIOHs and SPS. These pins are the reference clock inputs for the PLL that supplies clocks to the core and I/Os. LVHSTL signaling is used. Lengths of processor bus clock traces must be matched to ensure the processors node bus I/Os are in-phase.
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Clocking Each Clock Generator requires two phase difference signals from each RAC within the SNC. The SNC provides a SYNCLK/PCLKN pair for each main channel. The PCLK and SYNCCLK divider must be cleared by reset to guarantee determinism. For each main channel, the SNC provides a clock (RxSCK) for serial operations. This clock is normally 1 MHz, but will change to the SYNCLK frequency (100 MHz) for specific operations.
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Clocking 7.8 JTAG The external TCK is synchronized to the internal core clock for interfacing to the TAP controller private chains. A metastability-hardened synchronizer is provided for this purpose. TCK interface to boundary scan uses TCK directly. TCK can be active 10 ms after RESET deassertion. When inactive, TCK should be deasserted (low). TCK can be clocked from 1 to 20 MHz. The TCK high time is a minimum of five BUSCLK cycles in duration.
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Clocking 7-6 Intel® E8870 Scalable Node Controller (SNC) Datasheet
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8 System Reset 8.1 Reset Types The Intel E8870 chipset supports several reset types. Table 8-1 describes their causes, characteristics and the sequences they trigger. describes these sequences in detail. Table 8-1. Intel® E8870 chipset Reset Types Reset Type Power-up Reset Section 8.2.1 Hot-Plug Power-up Section 8.2.1 Triggered by Description System power logic or reset button results in PWRGOOD assertion. This must be followed by a RESETI# deassertion.
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System Reset 8.2 Reset Sequences All E8870 chipset reset sequences with the sub-sequences are summarized in Table 8-2. Table 8-2. Sequence PWRGOOD Deassertion PWRGOOD Assertion Reset Response Sequences Summary Begins Ends SNC When PWRGOOD falls or as the power rails rise. (not possible to define behavior prior to power supplies in spec) System Logic asserts PWRGOOD PWRGOOD rises. Internal clocks not stable yet.
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System Reset 8.2.1 Power-up Reset Sequence The following sections define the timing required of external E8870 chipset signals at power-up. The power-up sequence is described in 3 phases: PWRGOOD deassertion, PWRGOOD assertion, and hard reset deassertion. Each component must see this timing at power-up, although they may not see the sequence at the same time.
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System Reset Table 8-3. Power-up and Hard Reset Deassertion Timings Description Min Max Comments T1 Power stable to PwrGood active 10ms As close to 10ms as possible. T3 PWRGOOD assertion to RESETI# deassertion 1ms 2ms T4 RESETI# deassertion to RESET66# deassertion 4002 SYSCLKs 4007 SYSCLKs Variation is due to alignment of 66 MHz clocks and SYSCLK. T5 RESETI# deassertion to processor RESET# deassertion. 200,000 SYSCLKs 200,000 SYSCLKs Meets 1ms minimum Pulse width.
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System Reset 8.2.1.1 PWRGOOD Deassertion While PWRGOOD is deasserted, the SNC asserts RESET# to processors and LRESET# to the LPC interface asynchronously. The SIOH asserts RESET66# asynchronously. Since internal clocks will not be within specifications while PWRGOOD is deasserted, PWRGOOD must act asynchronously. All E8870 chipset components will reset any core logic that can be asynchronously reset, and all logic must be forced into a non-destructive state.
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System Reset rising edge makes setup and hold at each component, the counters will all have the same phase relationship on each power-up. Figure 8-3 shows how this sampling guarantees that RESETO# from any SNC will produce the same hard reset deassertion phasings in each component. Figure 8-3.
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System Reset Figure 8-4.
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System Reset 8.2.2.2 Hard Reset Assertion that Does Not Preserve Memory nor Configuration As the default value of SAVMEM is 0, power-up reset follows this path. Internal clocks are not stable when PWRGOOD rises, so these actions are not guaranteed to immediately take effect. However, the clocks will become stable long enough before RESETI# rises for these actions to succeed.
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System Reset CLK66 and CLK33 references are reset only on the First Reset deassertion. After a delay to allow CLK33 and CLK66 to stabilize, the SIOH deasserts RESET66# and initiates the ICH4 CPURST handshake sequence. Subsequent resets have no effect on these clocks. SP initialization and framing is started. SPs are enabled in all components except SNCs with local firmware and processors attached. SP framing will not complete until software enables those SPs. The SNC holds off processor requests.
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System Reset • After Multi-cycle initialization is complete, If ((MC.MT indicated DDR before the reset) OR (this is the First Reset Deassertion after PWRGOOD)), Pulse MEMRST# to invalidate any writes buffered in the DMH. 8.2.2.6 Deterministic Hard Reset The E8870 chipset behavior following the first RESETI# deassertion will not necessarily be repeatable. The E8870 chipset guarantees determinism only from resets triggered by a configuration write to the system hard reset bit in the SNC SYRE register.
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System Reset DDR-SDRAM refresh is not synchronized to the memory maintenance cycle. The DDR refresh counter in the SNC will be cleared on hard reset deassertion to maintain determinism. In the worst case, this can double one refresh interval. Since refreshes rotate across the 16 possible DIMM sides, a given DIMM side may experience a refresh interval 17/16ths longer than usual. To guarantee that each DIMM side receives one refresh every 15.
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System Reset 8.2.2.8 Itanium® 2 Processor BINIT# Reset A BINIT# assertion on the Itanium 2 processor bus triggers a hard reset assertion sequence followed by a hard reset deassertion sequence in the SNC. The hard reset assertion sequences results in the processor and SP buses being blocked while outstanding memory accesses are completed. RESET# and associated processor power-up configuration values are not driven. BNR# is deasserted when the memory maintenance cycle is complete.
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System Reset Figure 8-7. Simplest Power Good Distribution SPSs SNCs Processors DMHs PWRGOOD PWRGOOD PWRGOOD PWRGOOD PWRGOOD SIOHs PWROK DET ICH4s Power Good Logic 8.3.1 ICH4: PWROK This pin causes the ICH4 to assert PCIRST#. It may be connected to PWRGOOD pins of all E8870 chipset components (as illustrated in Figure 8-7), or the result of an OR of PWRGOOD, SNC RESETO# pins, or other sources of hard reset (as illustrated by Figure 8-8).
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System Reset Figure 8-8. Basic System Reset Distribution SPSs DET Processor Processor RESET# RESET# SIOHs RESET66# CPURST# RESETI# P64Hs SNCs LPCRST# LPC RESETO# MEMRST# PCIRST# DMH PCI P64H Agents P64H P64H PCIRST# ICH4 PWROK PWRGOOD from Power supplies Other Resets Figure 8-9. Basic System Reset Timing SYSCLK CLK33, CLK66 SPS, SIOH, SNC: PWRGOOD >4000 SYSCLK ICH4: PWROK ICH4: PCIRST#, SPS, SNC, SIOH: RESETI# >1ms ~4000 SYSCLK (T4+T9) SIOH: RESET66# Hub Interface to ICH4 8.3.
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System Reset 8.3.6 SIOH: RESET66# This pin is asserted combinationally while RESETI# is asserted or asynchronously after PWRGOOD assertion, or if the hard reset bit is set in the SIOH SYRE register. RESET66# will rise synchronously to CLK66. This pin will be driven to the P64H2 RSTIN# pin. 8.3.7 P64H2: RSTIN# The SIOH drives this with RESET66#. All P64H2 logic is cleared synchronously when RSTIN# is asserted. 8.3.
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System Reset 8.3.13 SNC: BNR# The SNC toggles BNR# to prevent requests from being initiated on the processor bus until the E8870 chipset initialization is complete. 8.3.14 SNC: BINIT# In the SNC, this pin initiates the reset described in Section 8.2.2.8, “Itanium® 2 Processor BINIT# Reset”. 8.3.15 SNC: INIT# Asserting the INIT# signal to the processors forces them to start execution at the boot vector.
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9 Electrical Specifications 9.1 Non-operational Maximum Rating The absolute maximum non-operational DC ratings are provided in Table 9-1. T. Functional operation at the absolute maximum and minimum ratings is neither implied nor guaranteed. The SNC should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and operational DC tables.
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Electrical Specifications Table 9-2. Voltage and Current Specifications (Continued) Symbol Parameter Min Typical Max Unit 1.71 1.8 1.89 V Notes Memory main channel Interface VCCRIO Termination Voltage Irio Termination Current 650 mA dIrio/dt Transient Slew Rate 0.025 A/ns 1.391 V j,k,l Scalability Port h Interfacei VCCSP Scalability Port Supply Voltage Isp Scalability Port Current 0.50 A m,n dIsp/dt Transient Slew Rate 1.0 A/ns o 3.3 3.465 V p 140 230 mA 0.
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Electrical Specifications AGTL+ inputs use differential receivers which require a reference signal (Vref). The SNC generates Vref on-die so there is no need for external logic. 9.3.2 Signal Group Table 9-3 contains the SNC system bus signals that are combined into groups by buffer type and whether they are inputs, outputs, or bidirectional with respect to the SNC. Most of the system bus signals use assisted gunning transceiver logic (AGTL+) signaling technology.
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Electrical Specifications c. d. e. f. g. 9.3.3 VTTMK, the system bus termination voltage. See Table 9-2. PLL analog voltage input. Connect to 1.5V ±5% supply on the motherboard through a network filter. Connect 1K Ohm, 1%, 0.1W, resistor across the FSBSLWCRES0 and FSBSLWCRES1. Connect 86.7 Ohm 1%, 0.1 W, resistor across the FSBODTCRES0 and FSBODTCRES1. DC Specifications The DC specifications for all the system bus interface signals are contained in Table 9-4. Table 9-4.
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Electrical Specifications Table 9-5. Scalability Port Interface Signal Group (Continued) Signal CMOS1.3 INPUTa SPxPRES CMOS1.3 I/O a SPxSYNC Power/Other VCCSP b, VSS Analog I/O c SPxZUPD[1:0]d, SPxAVREFH[3:0], SPxBVREFH[3:0], SPxAVREFL[3:0], SPxBVREFL[3:0]e SP Analog Input VCCASPe, VSSASP a. b. c. d. e. 9.5 Signal Description See Section 9.8 for “CMOS1.3” specifications. VCCSP is to be supplied to the SP port externally. See Table 9-2. Reference voltages are generated on-die.
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Electrical Specifications 9.5.2 DC Specifications Table 9-8. RSL Data Group, DC Parameters (a, b) Symbol Parameter Min Max Unit Notes Vil Input Low Voltage Vref,r – 0.5 Vref,r – 0.175 V c Vih Input High Voltage Vref,r + 0.175 Vref,r + 0.5 V c VDIS Data Voltage Swing 0.54 1.10 V ADI Data Input Asymmetry about VREF –15% 15% VDIS Iol Output Low Current 30 mA Ili Input Leakage Current 5 µA Ilo Output Leakage Current 5 µA a. b. c. d.
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Electrical Specifications 9.6 LPC Signal Group The seven required and five supporting signals used for the low pin count (LPC) interface are listed in the following table. Many of the signals are the same as signals found on the PCI interface. Table 9-11. LPC Interface Signal Group Signal Group Signal LPC I/O LAD[3:0] LPC Output LFRAME#, LRESET#, LPCCLKOUT[2:0] LPC Input LCLK CMOS 1.5 Input a. 9.6.1 a LPCSEL, LPCEN See Section 9.8 for CMOS 1.5V specifications. DC Specifications Table 9-12.
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Electrical Specifications For specifications related to components or external tools that will interface with the SNC components, refer to that component or tool’s associated specification. Table 9-13. SMBus and TAP Interface Signal Group Signal Group Signal SMBus (I/O) SPDCLK, SPDDA, SCL, SDA TAP (Input) TCK, TDI, TMS, TRST# TAP (Output) TDO Table 9-14. TAP Signal Terminationsa,b TCK 27-ohm to GND TMS 39-ohm to VCC TDIc 150-ohm to VCC TDO, TDI 75-ohm to VCC TRST# 500 to 680-Ohm to GND a.
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Electrical Specifications Figure 9-1. TAP DC Thresholds VT+ (max) VT+ (min) TAP Signal VH (min) VT - (max) VT- (min) VH (min) Table 9-16. SMBus DC Parametersa,b Symbol Mi Max Unit Vil Input Low Voltage –0.5 0.8 V Vih Input High Voltage 2.1 3.47 V Vol Output Low Voltage 0.4 V Ili Input Leakage Current 50 µA Ipullup Current through Pull-up Resistor Cin Input Capacitance Vnoise Signal Noise Immunity a. b. c. d. e. 9.7.2 Parameter 4.
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Electrical Specifications Table 9-18. TAP Signal Group AC Specificationsa Symbol Minimum Maximum Unit Figure TCK Frequency 1.0 20 MHz 9-3 T58 TCK, TMS, TDI Rise Time 0.5 16 ns 9-3 T59 TCK, TMS, TDI Fall Time 0.5 16 ns b TDO Rise Time 2.3 4.6 ns b TDO Fall Time 1.2 5.3 ns b T60 TDO Clock to Output Delay 2.5 10 ns 9-2 c T61 TDI, TMS Setup Time 5 ns 9-2 d,e T62 TDI, TMS Hold Time 18 ns 9-2 d,e TRST# Assert Time 300 ns a. b. c. d.
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Electrical Specifications Figure 9-3. TCK and SM_CLK Clock Waveform TTr r TThh **VV22 Clock Clock **VV11 TTf f TTl l TTpp Tr Tf Th Tl Tp = = = = = T58, T74 (Rise Time) T59, T75 (Fall Time) T72 (High Time) T73 (Low Time) T55 (TCK, SM_CLK Period) V1, V2: For rise and fall times, TCK and SM_CLK are measured between 20% and 80% points. 9.8 Miscellaneous Signal Pins All buffer types that do not belong to one of the major buses in the system are listed as miscellaneous signals. 9.8.
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Electrical Specifications 9.8.2 DC Characteristics Table 9-20. CMOS 1.3V DC Parametersa,b Symbol Parameter Min Max Unit Notes Vil Input Low Voltage –0.3 0.35 V Vih Input High Voltage 1.11 VCCSP + 0.3 V Vol Output Low Voltage –0.15 0.26 V c Voh Output High Voltage 1.21 1.39 V c Ili Input Leakage Current 10 µA Ron_p On-resistance p-device 300 700 Ohm Ron_n On-resistance n-device 27 72 Ohm Min Max Unit a. b. c. All specifications are at the pin of the package.
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Electrical Specifications Table 9-23. CMOS 1.8V Output DC Parametersa Symbol Parameter VoH Output High Voltage VoL Output Low Voltage Ron Output Impedance, Pull-down Ron Output Impedance, Pull-up Ili Input Leakage current a. Min Max Unit 0.20 V 40 ohm 24 40 ohm –500 500 µA Min Max Unit 2.0 VCC + 0.3 V 0.50 1.50 20 Notes V Supply voltage at 1.5V ±5% tolerance. Table 9-24. CMOS 3.3V DC Parameters Symbol VIH 9.8.3 Parameter Input High Voltage VIL Input Low Voltage –0.
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Electrical Specifications Table 9-27. CMOS 1.5V AC Parametersa,b Symbol Tco Parameter Clock to Output Valid Delay Min Max Unit Notes –0.28 1.44 ns c Tsu Input Setup Time 0.84 ns Thold Input Hold Time 0.35 ns SRf Output Slew Rate Fall 2.00 5.00 V/ns SRr Output Slew Rate Rise 1.90 4.9 V/ns 1.35 ns Max Unit 6.45 ns Signal: RESETO# Tco a. b. c. Clock to Output Valid Delay Supply voltage at 1.5V ±5% tolerance. Clock delay is in reference to the 200 MHz clock.
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Electrical Specifications Table 9-30. CMOS 3.3 V AC Parametersa,b (Continued) Symbol Min Max Unit SRf Output Slew Rate Fall 1 4 V/ns SRr Output Slew Rate Rise 1 4 V/ns a. b. 9.9 Parameter Notes Supply voltage at 1.5V ±5% tolerance. Clock delay is in reference to the 200 MHz clock. Clock Signal Groups Table 9-31. Clock Signal Groups Signal Group Signals LVHSTL Differential Inputs BUSCLK, BUSCLK# Table 9-32. LVHSTL Clock DC Parameters Symbol 9.9.
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Electrical Specifications Figure 9-4.
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10 Ballout and Package Information 10.1 1357-ball OLGA2b Package Information The 1357-ball OLGA2b package has an exposed die mounted on a package substrate. The package’s coplanarity has a mean of approximately 8 mils and a tolerance at 4-sigma of approximately 4 mils. A heatsink, with appropriate interface material and retention capabilities, is required for proper operation. Figure 10-1. 1357-ball OLGA2b Package Dimensions – Top View Handling Exclusion Area Die Keepout Area 0.914in. 0.614in. 0.100in.
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Ballout and Package Information Figure 10-2. 1357-ball OLGA2b Package Dimensions – Bottom View AU AT AR AP AN AM AL AK AJ AH AG AF AE AD 1.27 AC AB AA Y W V U T R P N M 24.765 L K J H G F E 1.27 D C B A A- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1.27 22.86 2X 1.905 MIN -B- 45.72 0.20 A B NOTE: All dimensions are in millimeters.
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Ballout and Package Information Figure 10-3. 1357-ball OLGA2b Solder Balls Detail OLGA SUBSTRATE D IE 2.140 +/- 0.150 NOTE: All dimensions shown here are estimations. 10.2 Ball-out Specifications 10.2.1 Ball-out Lists Table 10-1 list the respective ball-outs and Table 10-2 the respective signal lists for SNC. All ball locations marked “N/C” are no-connects. All ball locations marked “RSVD” are reserved. Both of these ball location types must remain unconnected.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1. SNC Ball List (Continued) Ball Number AF16 10-16 Signal N/C Ball Number AG18 Signal VSS AF17 VSS AG19 LAD[3] AF18 N/C AG20 VCC3.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-1.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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Ballout and Package Information Table 10-2.
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11 Testability The SNC implements the Test Access Port (TAP) logic for testability purpose. The TAP complies with the IEEE 1149.1 (JTAG) specification. Basic Functionality of the 1149.1-compatible test logic is described here., but this document does not describe the IEEE 1149.1 standard in detail. For details of the IEEE 1149.1 Specification, the reader is referred to the published standard1, and to other industry standard material on the subject.
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Testability A simplified block diagram of the TAP used in the this chipset components is shown in Figure 11-2. This TAP logic consists of a finite state machine controller, a serially-accessible instruction register, instruction decode logic, and data registers. The set of data registers includes those described in the 1149.1 standard (the bypass register, device ID register, etc.), plus chipsetspecific additions. The private data registers used to control the test and debug features are not shown.
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Testability Figure 11-3.
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Testability • Select-DR-Scan: This is a temporary controller state and all test data registers selected by the current instruction retain their previous values. • Capture-DR: In this state, data may be parallel-loaded into test data registers selected by the current instruction on the rising edge of TCK. If a test data register selected by the current instruction does not have a parallel input, or if capturing is not required for the selected test, then the register retains its previous state.
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Testability Table 11-2. Public TAP Instructions (Continued) Instruction Encoding Data Register Selected Description The SAMPLE/PRELOAD Instruction is used to allow scanning of the boundary-scan register without causing interference to the normal operation of the device. Two functions can be performed by use of the Sample/Preload Instruction.
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Testability TDI and TDO. The bypass register is selected when no test operation is being performed by a component on the board. The bypass register loads a logic zero at the start of a scan cycle. 3. Device Identification (ID) Register The device ID register contains the manufacturer’s identification code, version number, and part number. The device ID register has a fixed length of 32 bits, as defined by the IEEE 1149.1 specification. 4.
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Testability Table 11-4. Example of Configuration Access Data Register Format (Continued) JCONF encode: 1000010 Bit Attr Default Description Status: 7:4 RW 0h [7]: Error bit set when a config request returns a Hard Fail condition. [6:5]: Reserved [4]: Busy bit. Set when read or write operation is in progress. Command: 0xxx = NOP used in polling the chain to determine if the unit is busy.
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Testability 11-8 Intel® E8870 Scalable Node Controller (SNC) Datasheet