Specifications

FC protocol, version 1, M68HC908 implementation
Developer’s Serial Bootloader, Rev. 13
Freescale Semiconductor 17
3.5 M68HC08 system limitations
This section summarizes limitations that must be considered when using the bootloader with the user
application.
3.5.1 Memory occupied
One of the most important requirements is to use the smallest code possible. Typical M68HC908
implementations are between 300 to 500 bytes, including the bootloader user table. If the target M68HC08
MCU is capable of FLASH programming using internal ROM routines, the memory consumption is near
the lower limit. Larger M68HC08 MCUs (which are not usually equipped with ROM code for FLASH
programming) will require approximately 500 bytes of FLASH of the total 32 KB (as is the case with the
MC68HC908GP32).
The bootloader is placed at the upper end of FLASH memory; therefore, the only modification required in
the user code is in the memory mapping (typically found in the linker parameter file).
The M68HC08 MCU signals the actual available FLASH addresses. The PC Bootloader software will not
allow programming if the user code overlaps with bootloader code.
3.5.2 Time delay upon startup and initial communication
The number of pins with specific meanings during bootloader startup must be as small as possible.
Especially in communication systems (for example, those using a standard serial port), pin overhead is
zero and a “certain level character at a certain time” method is used. So, the bootloader waits a certain
amount of time to receive an answer from the PC at startup. If none is received, the user code starts. The
typical delay is in the range of several hundred milliseconds.
If this startup delay becomes an issue for the final application, the user may modify the bootloader code
and use a “certain level on a certain pin” method instead. A simple test of the voltage level on the IRQ pin
(or any other input pin) can be used to indicate whether the bootloading sequence is required.
3.5.3 Each interrupt 3T delayed
Every interrupt call is delayed by 3T bus clocks required to execute the JMP instruction stored in the
bootloader user table. This interrupt vector relocation (as described in Interrupt vector table relocation) has
been chosen as the best solution for achieving user code transparency and security of the bootloader code.
The interrupt latency is about 10 to 15T (assuming that no interrupt is being executed), so this additional
delay is not significant for the most applications.
3.5.4 FLBPR not usable (in some M68HC08 family MCUs)
The bootloader uses a FLASH block protection technique to protect itself from being overwritten (where
applicable; see FLASH Block Protection Register (FLBPR) for details).
Some M68HC08 MCUs (such as the KX, GP, and GR devices) have this FLASH block protection register
stored in FLASH, so it cannot be modified in user mode. The FLBPR can be erased or programmed only