User`s manual

23 // CHANGES FOR BOARD REVISION 003
24 //
25 // 1) Combined flash chip enables into a single signal, flash_ce_b.
26 //
27 // CHANGES FOR BOARD REVISION 002
28 //
29 // 1) Added SRAM clock feedback path input and output
30 // 2) Renamed "mousedata" to "mouse_data"
31 // 3) Renamed some ZBT memory signals. Parity bits are now incorporated into
32 // the data bus, and the byte write enables have been combined into the
33 // 4-bit ram#_bwe_b bus.
34 // 4) Removed the "systemace_clock" net, since the SystemACE clock is now
35 // hardwired on the PCB to the oscillator.
36 //
37 ///////////////////////////////////////////////////////////////////////////////
38 //
39 // Complete change history (including bug fixes)
40 //
41 // 2006-Mar-08: Corrected default assignments to "vga_out_red", "vga_out_green"
42 // and "vga_out_blue". (Was 10’h0, now 8’h0.)
43 //
44 // 2005-Sep-09: Added missing default assignments to "ac97_sdata_out",
45 // "disp_data_out", "analyzer[2-3]_clock" and
46 // "analyzer[2-3]_data".
47 //
48 // 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
49 // actually populated on the boards. (The boards support up to
50 // 256Mb devices, with 25 address lines.)
51 //
52 // 2004-Oct-31: Adapted to new revision 004 board.
53 //
54 // 2004-May-01: Changed "disp_data_in" to be an output, and gave it a default
55 // value. (Previous versions of this file declared this port to
56 // be an input.)
57 //
58 // 2004-Apr-29: Reduced SRAM address busses to 19 bits, to match 18Mb devices
59 // actually populated on the boards. (The boards support up to
60 // 72Mb devices, with 21 address lines.)
61 //
62 // 2004-Apr-29: Change history started
63 //
64 ///////////////////////////////////////////////////////////////////////////////
65
66 module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
67 ac97_bit_clock,
68
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