User`s manual

12
13 Script runs through a coe file (basically row after row of 8 bit values) and
14 sends line by line.
15 ’’’
16
17 ser = serial.Serial(port=’/dev/tty.usbserial-FTDHKA57’)
18
19 a = open(’audio_convert/Fa48k8bit.coe’,’r’)
20
21 for line in a:
22
23 line = line.rstrip()[0:-1]
24 line = int(line, base=2)
25
26 b = struct.pack("<H", line)
27
28 r = ser.write(b[0])
29
30 ser.close()
A.2 Labkit
A.2.1 labkit.v
1 ‘default_nettype none
2 ////////////////////////////////////////////////////////////////////////////////
3 //
4 // 6.111 FPGA Labkit -- Template Toplevel Module
5 //
6 // For Labkit Revision 004
7 //
8 //
9 // Created: October 31, 2004, from revision 003 file
10 // Author: Nathan Ickes
11 //
12 ///////////////////////////////////////////////////////////////////////////////
13 //
14 // CHANGES FOR BOARD REVISION 004
15 //
16 // 1) Added signals for logic analyzer pods 2-4.
17 // 2) Expanded "tv_in_ycrcb" to 20 bits.
18 // 3) Renamed "tv_out_data" to "tv_out_i2c_data" and "tv_out_sclk" to
19 // "tv_out_i2c_clock".
20 // 4) Reversed disp_data_in and disp_data_out signals, so that "out" is an
21 // output of the FPGA, and "in" is an input.
22 //
88