User`s manual

518 endmodule

A.1.12 usb input.v

1 //reads data and puts it on out

2 module usb_input(clk,reset,data,rd,rxf,out,newout,hold,state);

3 input clk, reset; //clock and reset

4 input [7:0] data; //the data pins from the USB fifo

5 input rxf; //the rxf pin from the USB fifo

6 output rd; //the rd pin from the USB fifo

7 reg rd;

9 output[7:0] out; //this is where data goes when it has been read from the fifo

10 reg[7:0] out;

11 output newout; //when this is high, out contains a new chunk of data

12 reg newout;

13 input hold; //as long as hold is high, this module sits

14 //still module and will not accept new data from the fifo

16 output state; //for debugging purposes

17 reg[3:0] state;

19 parameter RESET = 0; //state data

20 parameter WAIT = 1;

21 parameter WAIT2 = 2;

22 parameter WAIT3 = 3;

23 parameter DATA_COMING = 4;

24 parameter DATA_COMING_2 = 5;

25 parameter DATA_COMING_3 = 6;

26 parameter DATA_COMING_4 = 7;

27 parameter DATA_COMING_5 = 8;

28 parameter DATA_HERE = 9;

29 parameter DATA_LEAVING =10;

30 parameter DATA_LEAVING_2=11;

31 parameter DATA_LEAVING_3=12;

32 parameter DATA_LEAVING_4=13;

33 parameter DATA_LEAVING_5=14;

34 parameter DATA_LEAVING_6=15;

36 initial

37 state <= WAIT;

39 always @ (posedge clk)

40 if(reset)

41 begin

42 newout <= 0;