User`s manual

39
40 wire flash_busy; //except these, which are internal to the interface
41 wire[15:0] fwdata;
42 wire[15:0] frdata;
43 wire[22:0] address;
44 wire [1:0] op;
45
46 reg [1:0] mode;
47 wire fsm_busy;
48
49 reg[2:0] state; //210
50
51 output[11:0] fsmstate;
52 wire [7:0] fsmstateinv;
53 assign fsmstate = {state,flash_busy,fsm_busy,fsmstateinv[4:0],mode}; //for debugging only
54
55 //this guy takes care of /some/ of flash’s tantrums
56 flash_int flash(reset, clock, op, address, fwdata, frdata, flash_busy, flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_sts, flash_byte_b);
57 //and this guy takes care of the rest of its tantrums
58 test_fsm fsm (reset, clock, op, address, fwdata, frdata, flash_busy, dots, mode, fsm_busy, wdata, raddr, fsmstateinv);
59
60 parameter MODE_IDLE = 0;
61 parameter MODE_INIT = 1;
62 parameter MODE_WRITE = 2;
63 parameter MODE_READ = 3;
64
65 parameter HOME = 3’d0;
66 parameter MEM_INIT = 3’d1;
67 parameter MEM_WAIT = 3’d2;
68 parameter WRITE_READY= 3’d3;
69 parameter WRITE_WAIT = 3’d4;
70 parameter READ_READY = 3’d5;
71 parameter READ_WAIT = 3’d6;
72
73 always @ (posedge clock)
74 if(reset)
75 begin
76 busy <= 1;
77 state <= HOME;
78 mode <= MODE_IDLE;
79 end
80 else begin
81 case(state)
82 HOME://0 //we always start here
83 if(!fsm_busy)
84 begin
71