User`s manual

22 reg [1:0] lop;

23 reg [15:0] rdata;

24 reg busy;

25 reg [15:0] flash_wdata;

26 reg flash_ddata;

27 reg [23:0] flash_address;

28 reg flash_oe_b, flash_we_b, flash_reset_b;

30 assign flash_ce_b = flash_oe_b && flash_we_b;

31 assign flash_byte_b = 1; // 1 = 16-bit mode (A0 ignored)

33 assign flash_data = flash_ddata ? flash_wdata : 16’hZ;

35 initial

36 flash_reset_b <= 1’b1;

38 reg [9:0] state;

40 always @(posedge clock)

41 if (reset)

42 begin

43 state <= 0;

44 flash_reset_b <= 0;

45 flash_we_b <= 1;

46 flash_oe_b <= 1;

47 flash_ddata <= 0;

48 busy <= 1;

49 end

50 else if (flash_reset_b == 0)

51 if (state == reset_assert_cycles)

52 begin

53 flash_reset_b <= 1;

54 state <= 1023-reset_recovery_cycles;

55 end

56 else

57 state <= state+1;

58 else if ((state == 0) && !busy)

59 // The flash chip and this state machine are both idle. Latch the user’s

60 // address and write data inputs. Deassert OE and WE, and stop driving

61 // the data buss ourselves. If a flash operation (read or write) is

62 // requested, move to the next state.

63 begin

64 flash_address <= {address, 1’b0};

65 flash_we_b <= 1;

66 flash_oe_b <= 1;