User`s manual

111 SAV_f2_cb0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y0;
112 SAV_f2_y0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_cr1;
113 SAV_f2_cr1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y1;
114 SAV_f2_y1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_cb0;
115
116 // These states are here in the event that we want to cover these signals
117 // in the future. For now, they just send the state machine back to SYNC_1
118 EAV_f1: current_state <= SYNC_1;
119 SAV_VBI_f1: current_state <= SYNC_1;
120 EAV_VBI_f1: current_state <= SYNC_1;
121 EAV_f2: current_state <= SYNC_1;
122 SAV_VBI_f2: current_state <= SYNC_1;
123 EAV_VBI_f2: current_state <= SYNC_1;
124
125 endcase
126 end
127 end // always @ (posedge clk)
128
129 // implement our decoding mechanism
130
131 wire y_enable;
132 wire cr_enable;
133 wire cb_enable;
134
135 // if y is coming in, enable the register
136 // likewise for cr and cb
137 assign y_enable = (current_state == SAV_f1_y0) ||
138 (current_state == SAV_f1_y1) ||
139 (current_state == SAV_f2_y0) ||
140 (current_state == SAV_f2_y1);
141 assign cr_enable = (current_state == SAV_f1_cr1) ||
142 (current_state == SAV_f2_cr1);
143 assign cb_enable = (current_state == SAV_f1_cb0) ||
144 (current_state == SAV_f2_cb0);
145
146 // f, v, and h only go high when active
147 assign {v,h} = (current_state == SYNC_3) ? tv_in_ycrcb[7:6] : 2’b00;
148
149 // data is valid when we have all three values: y, cr, cb
150 assign data_valid = y_enable;
151 assign ycrcb = {y,cr,cb};
152
153 reg f = 0;
154
155 always @ (posedge clk)
156 begin
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