User`s manual

24 reg old_frame; // frames are even / odd interlaced
25 reg even_odd; // decode interlaced frame to this wire
26
27 wire frame = fvh[2];
28 wire frame_edge = frame & ~old_frame;
29
30 always @ (posedge vclk) begin//LLC1 is reference
31
32 old_dv <= dv;
33 vwe <= dv && !fvh[2] & ~old_dv; // if data valid, write it
34
35 old_frame <= frame;
36 even_odd = frame_edge ? ~even_odd : even_odd;
37
38 if (!fvh[2]) begin
39 col <= fvh[0] ? COL_START :
40 (!fvh[2] && !fvh[1] && dv && (col < 1024)) ? col + 1 : col;
41 row <= fvh[1] ? ROW_START :
42 (!fvh[2] && fvh[0] && (row < 768)) ? row + 1 : row;
43 vdata <= (dv && !fvh[2]) ? din : vdata;
44 end
45 end
46
47 // synchronize with system clock
48
49 reg [9:0] x[1:0],y[1:0];
50 reg [29:0] data[1:0];
51 reg we[1:0];
52 reg eo[1:0];
53
54 always @(posedge clk)begin
55
56 {x[1],x[0]} <= {x[0],col};
57 {y[1],y[0]} <= {y[0],row};
58 {data[1],data[0]} <= {data[0],vdata};
59 {we[1],we[0]} <= {we[0],vwe};
60 {eo[1],eo[0]} <= {eo[0],even_odd};
61 end
62
63 // edge detection on write enable signal
64
65 reg old_we;
66 wire we_edge = we[1] & ~old_we;
67 always @(posedge clk) old_we <= we[1];
68
69 // shift each set of four bytes into a large register for the ZBT
42