User`s manual

10 module divider #(parameter WIDTH = 8)
11 (input clk, sign, start,
12 input [WIDTH-1:0] dividend,
13 input [WIDTH-1:0] divider,
14 output reg [WIDTH-1:0] quotient,
15 output [WIDTH-1:0] remainder,
16 output ready);
17
18 reg [WIDTH-1:0] quotient_temp;
19 reg [WIDTH*2-1:0] dividend_copy, divider_copy, diff;
20 reg negative_output;
21
22 assign remainder = (!negative_output) ?
23 dividend_copy[WIDTH-1:0] : ~dividend_copy[WIDTH-1:0] + 1’b1;
24
25 reg [6:0] bit;
26 reg del_ready = 1;
27 assign ready = (!bit) & ~del_ready;
28
29 wire [WIDTH-2:0] zeros = 0;
30 initial bit = 0;
31 initial negative_output = 0;
32 always @( posedge clk ) begin
33 del_ready <= !bit;
34 if( start ) begin
35
36 bit = WIDTH;
37 quotient = 0;
38 quotient_temp = 0;
39 dividend_copy = (!sign || !dividend[WIDTH-1]) ?
40 {1’b0,zeros,dividend} :
41 {1’b0,zeros,~dividend + 1’b1};
42 divider_copy = (!sign || !divider[WIDTH-1]) ?
43 {1’b0,divider,zeros} :
44 {1’b0,~divider + 1’b1,zeros};
45
46 negative_output = sign &&
47 ((divider[WIDTH-1] && !dividend[WIDTH-1])
48 ||(!divider[WIDTH-1] && dividend[WIDTH-1]));
49 end
50 else if ( bit > 0 ) begin
51 diff = dividend_copy - divider_copy;
52 quotient_temp = quotient_temp << 1;
53 if( !diff[WIDTH*2-1] ) begin
54 dividend_copy = diff;
55 quotient_temp[0] = 1’d1;
38