User`s manual

10 //
11 // 24-Sep-05 Ike: updated to use new reset-once state machine, remove clear
12 // 28-Nov-06 CJT: fixed race condition between CE and RS (thanks Javier!)
13 //
14 // This verilog module drives the labkit hex dot matrix displays, and puts
15 // up 16 hexadecimal digits (8 bytes). These are passed to the module
16 // through a 64 bit wire ("data"), asynchronously.
17 //
18 ///////////////////////////////////////////////////////////////////////////////
19
20 module display_16hex (reset, clock_27mhz, data,
21 disp_blank, disp_clock, disp_rs, disp_ce_b,
22 disp_reset_b, disp_data_out);
23
24 input reset, clock_27mhz; // clock and reset (active high reset)
25 input [63:0] data; // 16 hex nibbles to display
26
27 output disp_blank, disp_clock, disp_data_out, disp_rs, disp_ce_b,
28 disp_reset_b;
29
30 reg disp_data_out, disp_rs, disp_ce_b, disp_reset_b;
31
32 ////////////////////////////////////////////////////////////////////////////
33 //
34 // Display Clock
35 //
36 // Generate a 500kHz clock for driving the displays.
37 //
38 ////////////////////////////////////////////////////////////////////////////
39
40 reg [4:0] count;
41 reg [7:0] reset_count;
42 reg clock;
43 wire dreset;
44
45 always @(posedge clock_27mhz)
46 begin
47 if (reset)
48 begin
49 count = 0;
50 clock = 0;
51 end
52 else if (count == 26)
53 begin
54 clock = ~clock;
55 count = 5’h00;
32