User`s manual

trigger an incremental build that can complete on the order of seconds, synthesis
of FPGA hardware is a lengthy process, taking on the order of minutes or even
hours depending on the amount of logic. Our complete avoidance of Coregen
modules definitely served us well in this respect. We also consciously often
commented out unnecessary modules. This provided dual benefits:
• Much shorter synthesis times
• Ensuring that the bug is being isolated as much as possible.
Nevertheless, these two steps are certainly not sufficient in efficient debugging.
As such, we adopted a multi-pronged testing and debugging approach. Broadly
speaking, we used the following methods:
• Icarus Verilog test benches/verification
• Xilinx ModelSim test benches/verification
• Julia implementations/tests of algorithms
• Labkit I/O, e.g led’s, hex display, logic analyzer probes
• Staring at code/data-sheets
• Integration tests
7.1 Icarus Verilog test benches/verification
By far the most effective and efficient way of testing simple modules in our
experience was the use of Icarus Verilog. We are extremely grateful to a fellow
student Andres for posting a note on our online discussion forum (Piazza) re-
garding the benefits and use of Icarus Verilog. Defining and using test benches
through Icarus Verilog is extremely easy and efficient. In our experience, this
was most useful for verifying long and complicated chains of combinational logic,
such as mathematical algorithms. It was also very useful for checking the syntax
of our Verilog code. As an example of its utility, we found a bug with perspec-
tive params that originated from incorrect mixed use of signed and unsigned
arithmetic. The main drawbacks of Icarus Verilog are its lack of visualizations
of waveforms when invoked on the command line, and its decreasing utility with
complex state machines and other sequential logic. The first of these drawbacks
is addressed quite well by Xilinx ModelSim.
7.2 Xilinx ModelSim test benches/verification
ModelSim helped us to discover a bug in the staff-provided divider module.
We instantiated a 79-bit divider and were not getting correct results. When we
examined waveforms in ModelSim, we saw that the ready bit was being asserted
far fewer than 79 cycles after we started the division. Upon closer examination
of the module, it turned out that the counter the module was using to keep
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