User`s manual
223 end
224
225 endmodule
A.3.11 pixel map.v
1 ‘default_nettype none
2 ///////////////////////////////////////////////////////////////////////////////////////////////////
3 // pixel_map: This module performs the core perspective transformation
4 // It computes (X, Y) = ((p1*x+p2*y+p3)/(p7*x+p8*y+p9),
5 // (p4*x+p5*y+p6)/(p7*x+p8*y+p9)) given values pi (computed in
6 // perspective_params.v)
7 // The module also does the necessary pixel read form ntsc_buf, and writes the
8 // output to vga_buf
9 //
10 // Future work:
11 // 1) Note the huge bit width of the divider. This results in a ridiculous ~80
12 // clock cycles per pixel. Pipelining of 80 bit divider can’t be done in
13 // coregen, and will need to be done manually. It would be a nice feature,
14 // since this would enable a real time projector display as opposed to current
15 // ~1-2 frames per second
16 //
17 // 2) reduce bit widths: these bit widths are conservative, and mathematically
18 // guaranteed never to lose precision. Software indicates that I can lose up
19 // to 20 bits of precision, and still be ok. A careful analysis of this needs
20 // to be performed
21 ///////////////////////////////////////////////////////////////////////////////////////////////////
22 module pixel_map(input clk,
23 input signed[67:0] p1_inv,
24 input signed[68:0] p2_inv,
25 input signed[78:0] p3_inv,
26 input signed[67:0] p4_inv,
27 input signed[68:0] p5_inv,
28 input signed[78:0] p6_inv,
29 input signed[58:0] p7_inv,
30 input signed[59:0] p8_inv,
31 input signed[70:0] p9_inv,
32 input signed[78:0] dec_numx_horiz,
33 input signed[78:0] dec_numy_horiz,
34 input signed[70:0] dec_denom_horiz,
35 input[11:0] pixel_in,
36 output reg[11:0] pixel_out,
37 output[16:0] ntsc_out_addr,
38 output reg vga_in_wr,
39 output[16:0] vga_in_addr);
40
232