User`s manual

39 //
40 // Future improvements:
41 // 1)
42 // This module uses over 120 out of 144 available 18x18
43 // multipliers!!!
44 // By reducing bitwidths and avoiding needless multiplies, e.g shifting
45 // whenever multiplying by constant, resource utilization could be improved
46 // Even with those improvements, I estimate the need of at least 80-100 18x18
47 // multipliers to avoid precision loss
48 //
49 // 2)
50 // Right now, the intention is to run this module on a slow clock, since we
51 // don’t want the parameters to change mid-frame anyway.
52 // Thus, timing is never an issue right now.
53 // However, module is easily pipelined, if one needs to run at fast clock.
54 ///////////////////////////////////////////////////////////////////////////////////////////////////
55
56 module perspective_params(input clk,
57 input[9:0] x1,
58 input[8:0] y1,
59 input[9:0] x2,
60 input[8:0] y2,
61 input[9:0] x3,
62 input[8:0] y3,
63 input[9:0] x4,
64 input[8:0] y4,
65 // reason for the hardcoded numbers is FPGA limitations on
66 // multiplier bitwidths (s18 x s18 yields s35)
67 // Note: guaranteed, mathematically proven bitwidths are:
68 // forward: 36, 36, 44, 35, 35, 43, 24, 24, 33
69 // inverse: 68, 69, 79, 68, 69, 79, 59, 60, 71
70 output reg signed[67:0] p1_inv,
71 output reg signed[68:0] p2_inv,
72 output reg signed[78:0] p3_inv,
73 output reg signed[67:0] p4_inv,
74 output reg signed[68:0] p5_inv,
75 output reg signed[78:0] p6_inv,
76 output reg signed[58:0] p7_inv,
77 output reg signed[59:0] p8_inv,
78 output reg signed[70:0] p9_inv,
79 output reg signed[78:0] dec_numx_horiz,
80 output reg signed[78:0] dec_numy_horiz,
81 output reg signed[70:0] dec_denom_horiz);
82
83 // sign extensions
84 wire signed[10:0] sx1, sx2, sx3, sx4;
228