User`s manual

9 // unnecessary Coregen usage
10 //
11 // credits: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
12 ///////////////////////////////////////////////////////////////////////////////////////////////////
13 module bram(input wire a_clk,
14 input wire a_wr,
15 input wire[16:0] a_addr,
16 input wire[11:0] a_din,
17 input wire b_clk,
18 input wire[16:0] b_addr,
19 output reg[11:0] b_dout);
20
21 // Shared memory
22 reg[11:0] mem[76799:0];
23
24 // Port A
25 always @(posedge a_clk) begin
26 if (a_wr) begin
27 mem[a_addr] <= a_din;
28 end
29 end
30
31 // Port B
32 always @(posedge b_clk) begin
33 b_dout <= mem[b_addr];
34 end
35
36 endmodule
A.3.7 addr map.v
1 ///////////////////////////////////////////////////////////////////////////////////////////////////
2 // a simple module for mapping hcount and vcount to address in bram
3 // the math:
4 // bram is 320*240 = 76800 lines, 320 columns, and 240 rows
5 // each line of bram corresponds to one pixel
6 // currently, each line is 12 bits (4 pixels r, 4 pixels g, 4 pixels b)
7 // hcount and vcount are in the 640x480 space
8 // Thus, the desired address is: 320*(vcount/2) + (hcount/2)
9 // = (128 + 32)vcount + hcount/2
10 ///////////////////////////////////////////////////////////////////////////////////////////////////
11
12 module addr_map(input[9:0] hcount,
13 input[9:0] vcount,
14 output[16:0] addr);
15
222