User`s manual

turns out that the BRAM design can work equally well with either p
i
or pinv
i
.
However, at this point of the project, we had already started using pinv
i
and
did not want to take the risk of going back to p
i
. Computing both p
i
and pinv
i
takes up approximately 80 % of the 144 available 18x18 bit signed multipliers
on the FPGA. This may be easily reduced to around 20 % by eliminating the
computation of pinv
i
, something we would have done with additional time for
the project.
Note that the p
i
(or pinv
i
) may be scaled by an arbitrary constant, so without
loss of generality, we assumed that p
3
= 1. However, to avoid needless divisions,
in the actual solutions implemented on the FPGA, we scale all parameters to
ensure that they are all integers. The closed-form solution to the set of equations
(2) (as implemented on the FPGA) is given below:
p
7
= 3[(x
1
− x
4
)(y
2
− y
3
) + (y
1
− y
4
)(x
3
− x
2
)] (3)
p
8
= 4[(x
1
= x
2
)(y
3
− y
4
) + (x
4
− x
3
)(y
1
− y
2
)] (4)
d = x
4
(y
2
− y
3
) + x
2
(y
3
− y
4
) + x
3
(y
4
− y
2
) (5)
p
9
= 1920d (6)
p
3
= 1920x
1
d (7)
p
6
= 1920y
1
d (8)
p
1
= x
4
p
7
+ 3(x
4
− x
1
)d (9)
p
2
= x
2
p
8
+ 4(x
2
− x
1
)d (10)
p
4
= y
4
p
7
+ 3(y
4
− y
1
)d (11)
p
5
= y
2
p
8
+ 4(y
2
− y
1
)d (12)
pinv
1
= p
6
p
8
− p
5
p
9
(13)
pinv
2
= p
2
p
9
− p
3
p
8
(14)
pinv
3
= p
3
p
5
− p
2
p
6
(15)
pinv
4
= p
4
p
9
− p
6
p
7
(16)
pinv
5
= p
3
p
7
− p
1
p
9
(17)
pinv
6
= p
1
p
6
− p
3
p
4
(18)
pinv
7
= p
5
p
7
− p
4
p
8
(19)
pinv
8
= p
1
p
8
− p
2
p
7
(20)
pinv
9
= p
2
p
4
− p
1
p
5
(21)
d
x
= 639pinv
1
(22)
d
y
= 639pinv
4
(23)
d
d
= 639pinv
7
(24)
d
x
, d
y
, d
d
are a couple of parameters used to avoid multiplications in the ac-
tual mapping described by the perspective transformation (2). More precisely,
they allow clients of this module (such as pixel map in our case) to simply ex-
ecute a two dimensional loop over the image, incrementing/decrementing the
numerator and denominator on each iteration as opposed to performing a fresh
17