User`s manual

5.7 bram (Ganesh)
The bram module is a very simple true dual port memory module, with exactly
enough storage for a down-sampled frame (320x240) with 12 bit color depth
per pixel. By convention, the first port is always a write port, triggered by
a WE (write enable) signal. The second port is a read port. The ports have
their own individual address lines and clock signals in order to achieve the dual
ported-ness. The advantages of a dual port memory over a single port memory
were clear in our case, and have already been outlined. One more advantage
of a dual port memory is that the two ports can be driven at different clocks.
The only place where the dual ported abstraction breaks down is when one
tries to read and write to the same address simultaneously. It is clear that
there is no reasonable behavior in that case. Our design takes this into account,
and guarantees that at most one pixel in each frame stores a garbage value.
Given the large fraction of displays with at least one defective pixel, this is
an extremely minor issue. We initially used Xilinx’s proprietary IP Coregen
application to synthesize the BRAM (block random access memory) module.
However, in order to maximize portability and minimize the use of proprietary
files, we studied this a little more and found out that with the appropriate
Verilog code, Xilinx’s tools will automatically infer the presence of a BRAM.
This allowed us to use our own very simple BRAM implementation. It also
gave us one additional benefit: Coregen modules often take significantly longer
to synthesize as compared to inferred ones.
5.8 addr map (Ganesh)
The addr map is a critical single-line module that abstracts away memory ad-
dress computations, allowing one to address the correct location in memory by
providing the x coordinate and y coordinate locations. This is a pure combina-
tional logic module, with no synchronization to any clock. Essentially, it takes
in an x coordinate in [0, 639] and a y coordinate in [0, 479], and computes the
memory address in the 320x240 line BRAM buffer. This is achieved by taking
the integer part of a division by 2 of the x and y coordinates, followed by a
standard mapping of a 2 dimensional matrix address to a flat array, an exact
analog of manipulating a matrix that has been heap allocated in the C program-
ming language. We unfortunately had a somewhat subtle bug in our memory
address computation. At its core, it boils down to the fact that integer division
by two followed by a multiplication is not the same as multiplication followed
by integer division by two. Fortunately, we tested this early on, and noticed a
checkerboard pattern with horizontal stripes on the VGA display instead of a
neat checkerboard. The credit for finding that bug goes to our TA Jos´e.
5.9 slow clk (Ganesh, James)
The slow clk is a simple module that takes in a high frequency clock signal
(on the order of MHz) and generates a signal with a much lower frequency.
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