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98 reg signed [15:0] accum = 0;
99 reg [5:0] num_samples = 0;
100 reg signed [15:0] data_right_shift;
101
102 always @(*) begin
103 data_right_shift = {data[15], data[15], data[15], data[15],
104 data[15], data[15:5]};
105 end
106
107 always @(posedge clock) begin
108 if (reset) begin
109 accum <= 0;
110 num_samples <= 0;
111 offset <= 0;
112 end
113 else if (in_ready) begin
114 num_samples <= (num_samples == 6’d32) ? num_samples : num_samples + 1;
115 samples[offset] <= data_right_shift;
116 if (num_samples == 6’d32) begin
117 accum <= accum + data_right_shift - samples[offset];
118 end
119 else begin
120 accum <= accum + data_right_shift;
121 end
122 offset <= offset + 1;
123 end
124 end
125
126 assign avg = accum;
127 assign avg_ready = (num_samples == 6’d32) ? 1 : 0;
128 endmodule
129
130 /*
131 ready permanently asserted after initialization completed
132 acc operates completely with the slowed accelerometer clock
133 */
134 module acc(input clk /* system clock */ , sdo, reset,
135 output ncs, sda, scl, ready, output signed [15:0] x, y);
136 // TODO use state machine -- transition through all of the initiatialization states (each
137 // register), then rotate through the value reading states
138 // one cycle gap between states to allow for CS deassertion
139 parameter MEASURE_INIT = 0;
140 parameter X_READ = 1;
141 parameter Y_READ = 2;
142 reg[1:0] state = MEASURE_INIT; // TODO: set the right number of bits for this
143 reg[4:0] count = 0; // TODO: set the right number of bits for this
123