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52 output[W-1:0] par);
53 reg[W-2:0] par_reg = 0;
54
55 always @(posedge clk) begin
56 par_reg <= {par_reg[W-3:0], ser};
57 end
58
59 assign par = {par_reg, ser};
60 endmodule
61
62 /*
63 reduces the system clock by a factor of 6
64 */
65 module acc_clk(input clk /* system clock */ , output dev_clk);
66 parameter TICKS = 9;
67
68 reg [3:0] count = 0;
69 reg sig_reg = 0;
70
71 always @(posedge clk) begin
72 if (count == TICKS) begin
73 // flip at half period
74 sig_reg <= ~sig_reg;
75 count <= 0;
76 end
77 else begin
78 count <= count + 1;
79 end
80 end
81 assign dev_clk = sig_reg;
82 endmodule
83
84 /*
85 assert in_ready when a new datapoint is available, avg_ready will
86 be signalled after 32 data points have been folded into the average
87 */
88 module moving_avg(
89 input clock, in_ready, reset,
90 input signed [15:0] data,
91 output signed [15:0] avg,
92 output avg_ready
93 );
94 // circular buffer
95 reg signed [15:0] samples [31:0];
96
97 reg [4:0] offset = 0;
122