User`s manual
6 // Create Date: 16:26:11 11/16/2014
7 // Design Name:
8 // Module Name: acc
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 /*
22 output starts on same cycle start is asserted
23 high-order bits produced first
24 input only needs to be supplied on the cycle that start is high
25 produces zeros if input exhausted
26 assume W > 1
27 */
28 module par_to_ser #(parameter W=8)
29 (input clk /* device clock */ , input[W-1:0] par,
30 input start, output ser);
31 reg[W-1:0] par_reg = 0;
32
33 always @(posedge clk) begin
34 if (start) begin
35 par_reg <= {par[W-2:0], 1’b0};
36 end
37 else begin
38 par_reg <= {par_reg[W-2:0], 1’b0};
39 end
40 end
41
42 assign ser = start ? par[W-1] : par_reg[W-1];
43 endmodule
44
45 /*
46 output appears W-1 clock cycles after first serial bit sent
47 assume high-order bits are input first
48 assume W > 2
49 */
50 module ser_to_par #(parameter W=8)
51 (input clk /* device clock */ , input ser,
121