User`s manual

19 # 5) Reversed disp_data_in and disp_data_out signals, so that "out" is an
20 # output of the FPGA, and "in" is an input.
21 #
22 # CHANGES FOR BOARD REVISION 003
23 #
24 # 1) Combined flash chip enables into a single signal, flash_ce_b.
25 # 2) Moved SRAM feedback clock loop to FPGA pins AL28 (out) and AJ16 (in).
26 # 3) Moved rs232_rts to FPGA pin R3.
27 # 4) Moved flash_address<1> to AE14.
28 #
29 # CHANGES FOR BOARD REVISION 002
30 #
31 # 1) Moved ZBT_BANK1_CLK signal to pin Y9.
32 # 2) Moved user1<30> to J14.
33 # 3) Moved user3<29> to J13.
34 # 4) Added SRAM clock feedback loop between D15 and H15.
35 # 5) Renamed ram#_parity and ram#_we#_b signals.
36 # 6) Removed the constraint on "systemace_clock", since this net no longer
37 # exists. The SystemACE clock is now hardwired to the 27MHz oscillator
38 # on the PCB.
39 #
40 ###############################################################################
41 #
42 # Complete change history (including bug fixes)
43 #
44 # 2007-Aug-16: Fixed revision history. (flash_address<1> was actually changed
45 # to AE14 for revision 003.)
46 #
47 # 2005-Sep-09: Added missing IOSTANDARD attribute to "disp_data_out".
48 #
49 # 2005-Jan-23: Added a pullup to FLASH_STS
50 #
51 # 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
52 # actually populated on the boards. (The boards support up to
53 # 256Mb devices, with 25 address lines.)
54 #
55 # 2005-Jan-23: Change history started.
56 #
57 ###############################################################################
58
59 #
60 # Audio CODEC
61 #
62
63 NET "beep" LOC="ac19" | IOSTANDARD=LVDCI_33;
64 NET "audio_reset_b" LOC="ae18" | IOSTANDARD=LVTTL;
105