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Automatic Projector Tilt Compensation

System

Ganesh Ajjanagadde Shantanu Jain James Thomas

December 10, 2014

Abstract

We designed a system that corrects the input to a projector if it is

tilted so that its output appears unskewed. We read input from a NTSC

(National Television System Committee) video camera and store it in an

internal block memory. We then process the frame stored in memory

using a p erspective transformation to pre-warp the image that is sent to

the projector via a VGA (Video Graphics Array) signal. The parameters

of the perspective transformation are obtained from an accelerometer,

which senses two axes of tilt. This allows automatic keystone correction

in the two directions sensed by the accelerometer provided the output

screen is vertical. Our method also includes options for manual keystone

correction to any degree desired, for any projector and screen orientations.

For ease of manual correction, we provide the option of using a test pattern

(a checkerboard). We also play some useful audio for the percentage of

pixels kept by the transformation.

Summary of content (245 pages)

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Automatic Projector Tilt Compensation System Ganesh Ajjanagadde Shantanu Jain James Thomas December 10, 2014 Abstract We designed a system that corrects the input to a projector if it is tilted so that its output appears unskewed. We read input from a NTSC (National Television System Committee) video camera and store it in an internal block memory.
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Acknowledgments First and foremost, we would like to thank our 6.111 instructor Gim Hom for his tremendous patience, experience, and intuition regarding digital systems. This project would never have been possible without him, and countless number of times he saved our group a huge amount of time by some very crucial observations. Not only that, he also played a very important role in our choice of project topic. Initially, we were planning to create some sort of Bitcoin miner.
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Contents 1 Introduction 5 2 Previous Work 6 3 Module Architecture 3.1 Accelerometer interface . . . 3.2 Perspective transformation . 3.3 I/O (Input/Output) interface 3.4 Audio system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 8 8 8 4 Design Decisions 4.1 Use of 640 × 480 @60 Hz VGA 4.2 Use of NTSC Camera as Input 4.
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8 Future Work 27 9 Conclusion 28 A Source Code A.1 Staff Modules . . . . . . . . . A.1.1 debounce.v . . . . . . A.1.2 delay.v . . . . . . . . . A.1.3 display 16hex.v . . . . A.1.4 vga.v . . . . . . . . . A.1.5 divider.v . . . . . . . . A.1.6 ycrcb2rgb.v . . . . . . A.1.7 ntsc2zbt.v . . . . . . . A.1.8 video decoder.v . . . . A.1.9 flash int.v . . . . . . . A.1.10 flash manager.v . . . . A.1.11 test fsm.v . . . . . . . A.1.12 usb input.v . . . . . . A.1.13 usb transfer script.py A.2 Labkit . . . . . . .
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1 Introduction Due to the advances in semiconductor technology, today’s display projectors can incorporate fairly sophisticated digital processing algorithms for various enhancements to the visual appearance. Moreover, there is an increasing prevalence of portable projectors that benefit from fast, automated setup. One desired functionality is keystone/tilt correction.
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Finally, we also provide a useful voice output for the percentage of pixels kept after the perspective transformation (this is a lossy transformation in general). The audio is triggered by pressing a button on the FPGA kit. 2 Previous Work Given the practical importance of keystone correction, there has been significant research on doing automatic keystone correction. While Raskar and Beardsley [2001] and Sukthankar et al.
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Figure 2: Block Diagram Our keystone correction system can be divided into roughly four functional components: 1. Accelerometer interface 2. Perspective transformation 3. I/O (Input/Output) interface 4. Audio system Each functional component handles a specific collection of tasks, and is further broken down into a set of one or more modules. 3.1 Accelerometer interface The accelerometer presents a SPI interface for data transfer.
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uses the par to ser and ser to par modules to initialize the accelerometer and fetch x and y acceleration readings from it in a loop, averaging them using the moving avg module. 3.2 Perspective transformation The perspective transformation component is where all core computations are performed. The accel lut module accepts the accelerometer readings from the accelerometer as an index into a ROM (read-only memory) containing coordinates of four coordinates of a quadrilateral.
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low-level details of working with the flash. When the audio is triggered via an external button input, audioManager handles queuing up the appropriate set of tracks for sequential playback. The percentage of pixels used is an external input to audioManager from the pixels kept module. 4 Design Decisions There are several noteworthy design decisions. 4.1 Use of 640 × 480 @60 Hz VGA The first of them is the use of a 640 × 480 @60 Hz VGA display.
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memory, and has a single read/write cycle latency, as opposed to the multicycle latency of ZBT memory. However, the amount of block memory available on the FPGA is only 2.5 Mbits. This required sacrifice on image quality. We chose a combination of image down-sampling and color depth reduction. More specifically, we chose a 320x240 sized memory, with 12 bits per line (4 bit R, 4 bit G, 4 bit B).
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was already used for the manual correction system, there was no other way to display the percentage of pixels used without showing it on the projected screen, which we had earlier eliminated considering it was only useful to power users. The manual adjustment functionality relies on the user being able to select the corner to be manipulated via a set of switches.
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This module first initializes the accelerometer and then reads x and y acceleration values from it in a loop. The clock used for accelerometer communications is our 50 MHz system clock slowed by a factor of 20, which meets the the max clock frequency spec of 5 MHz. Most of the default configurations for the accelerometer are acceptable for our purposes; the only initialization we need to do is set the measure bit of the POWER CTL register (each register contains a single byte).
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registers is acceptable), and then wait 16 additional cycles for all of our data to be produced on the SDO line. We rotate between a state for reading the x registers and a state for reading the y registers. We feed the produced x and y readings into instantiations of the moving avg filter. The output of the acc module is the output of these filters. One challenge we faced was getting the accelerometer clock period correct.
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5.5 accel lut (Ganesh) The accel lut module provides a look-up table from the accelerometer readings in two directions to the four corners of the quadrilateral. The output is synchronized to the global sys clk. The module is essentially implemented as a giant case statement, from which Xilinx’s tools are able to infer a ROM of the appropriate size. Although the data coming out of the accelerometer has 10 bits of precision in each axis, using the full precision would require too much space for the ROM.
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5.7 bram (Ganesh) The bram module is a very simple true dual port memory module, with exactly enough storage for a down-sampled frame (320x240) with 12 bit color depth per pixel. By convention, the first port is always a write port, triggered by a WE (write enable) signal. The second port is a read port. The ports have their own individual address lines and clock signals in order to achieve the dual ported-ness.
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For us, this was of use in generating a clock with a frequency on the order of a Hz for synchronizing the quadrilateral corner locations and perspective transform parameters. It was also of use in generating a clock signal that met the manufacturer specs for the accelerometer (see the acc section). It is implemented by having a looping counter that would result in an inversion of the clock signal every time the counter hit a certain number of “ticks”.
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turns out that the BRAM design can work equally well with either pi or pinvi . However, at this point of the project, we had already started using pinvi and did not want to take the risk of going back to pi . Computing both pi and pinvi takes up approximately 80 % of the 144 available 18x18 bit signed multipliers on the FPGA. This may be easily reduced to around 20 % by eliminating the computation of pinvi , something we would have done with additional time for the project.
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multiplication. Essentially, they correspond to the decrements needed at the end of each horizontal scan line. Note the use of 480, 640 (i.e 1920 and 1920 4 4 ) as opposed to the more precise 479, 639. The reason for this is that 480, 640 are multiples of sizable powers of two, reducing the bit width needed for certain multiplications required in the solution. Moreover, the difference caused by this slight error can be ignored, due to the continuity of the perspective transformation.
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width of 32 bits, which is insufficient for our needs. Furthermore, they discourage creation of pipe-lined dividers of greater width due to the high area cost. As such, we require 80 clock cycles per pixel, resulting in a frame rate of 1-2 frames per second. Note that with sufficient hardware resources, this may be easily converted into a real-time system. 5.
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than the NTSC data was coming to us (the tv in line clock1 rate). This was causing some setup times at the BRAM to be violated when clocks were out of phase and the BRAM to be written with unstable values. Below is an image of the ntsc to bram code working in isolation: Figure 4: camera output using bram 5.14 audioManager (Shantanu) The audioManager module is the core module in the audio playback component.
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deleting its contents, which the labkit automatically does when it is powered on, the module also has a “reset disable” switch. When in “write mode”, the labkit prepares itself to receive data from the usb hardware, via the usb input module provided by the staff. Whenever usb input indicates a new data sample is available, the “dowrite” input to the staff provided flash manager module is asserted to be true, in order to trigger the write operation.
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ity to the user than the seemingly-opaque efficient algorithms, at the expense of utilizing more of the scarce look-up tables on the hardware.
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Figure 6: User Interface When pressed, button 0 triggers the audio system, which announces the percentage of screen pixels currently used for the corrected image. LEDs 7-1 show the binary representation of this value. Buttons 2 and 3 adjust the volume of the audio system up or down.
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trigger an incremental build that can complete on the order of seconds, synthesis of FPGA hardware is a lengthy process, taking on the order of minutes or even hours depending on the amount of logic. Our complete avoidance of Coregen modules definitely served us well in this respect. We also consciously often commented out unnecessary modules. This provided dual benefits: • Much shorter synthesis times • Ensuring that the bug is being isolated as much as possible.
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track of the current bit was only 6 bits wide, which supports only operand bit widths up to 63. We extended the width of this counter to 7 bits to solve this issue. ModelSim was also used to verify the functionality of the BCD module. After uncovering a bug in the percentage of pixels kept during integration, the first area of investigation was the BCD module, since it was the least tested module. It was trivial to write a test bench for the module and verify the output was correct using ModelSim. 7.
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It did not take us too long to realize the mistake in the implementation, and looking back we do not see any other way of correcting the mistake. As described in the section on the acc module, taking a second pass through the data-sheet for the accelerometer helped us to identify an issue with a violated timing constraint (tCS,DIS ). 7.6 USB input to flash memory issues The most challenging issue in the audio component of the project was receiving data over USB and storing the samples into flash memory.
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from 100 to get the correct value. The playback of the percentage was often incorrect for some reason (never identified). Initially, we were keen on fixing the issue from the audio end, since pixels lost was a known correct module. However, we had no luck fixing it from the audio end, so instead we renamed pixels lost to pixels kept and removed the subtraction from 100. This somehow fixed the issue. Much easier was the integration with the accelerometer.
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• Store the look-up table in a larger memory, e.g ZBT. • A more scalable approach is to start doing interpolation in the hardware itself. This will require additional hardware resources and more logic, but the size of the logic will only grow with the number of data points, as opposed to the number of bits coming from the sensors. Within the audio component, there are many avenues for substantial improvement.
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issues as early as possible, with a consistent time commitment every week. Second, we spent a lot of time doing software simulations/verifications before diving in and writing Verilog. The rationale behind this is that correction and testing in software is much faster than synthesis on the FPGA. Third, we had regular meetings among ourselves to ensure that issues some member of our team had would be addressed collectively.
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A Source Code Source code for the project may be obtained on GitHub: https://github.com/ gajjanag/6111_Project. For completeness, we include all source code here as well. For ease of browsing through the code, we have divided the modules into roughly three categories: • Staff Modules: modules that are essentially the same as staff provided modules, with minor modifications for our specific needs.
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A.1.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 delay.v ‘timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 23:13:26 12/02/2014 // Design Name: // Module Name: delay // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.
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10 11 12 13 14 15 16 17 18 // // 24-Sep-05 Ike: updated to use new reset-once state machine, remove clear // 28-Nov-06 CJT: fixed race condition between CE and RS (thanks Javier!) // // This verilog module drives the labkit hex dot matrix displays, and puts // up 16 hexadecimal digits (8 bytes). These are passed to the module // through a 64 bit wire ("data"), asynchronously.
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56 57 58 59 end else count = count+1; end 60 61 62 63 64 65 always @(posedge clock_27mhz) if (reset) reset_count <= 100; else reset_count <= (reset_count==0) ? 0 : reset_count-1; 66 67 assign dreset = (reset_count != 0); 68 69 assign disp_clock = ~clock; 70 71 72 73 74 75 //////////////////////////////////////////////////////////////////////////// // // Display State Machine // //////////////////////////////////////////////////////////////////////////// 76 77 78 79 80 81 82 reg reg reg reg reg re
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102 103 104 dot_index <= 0; state <= state+1; end 105 106 107 108 109 110 111 8’h01: begin // End reset disp_reset_b <= 1’b1; state <= state+1; end 112 113 114 115 116 117 118 119 120 121 122 8’h02: begin // Initialize dot register (set all dots to zero) disp_ce_b <= 1’b0; disp_data_out <= 1’b0; // dot_index[0]; if (dot_index == 639) state <= state+1; else dot_index <= dot_index+1; end 123 124 125 126 127 128 129 130 131 8’h03: begin // Latch dot data disp_ce_b <= 1’b1; dot_index <= 31; // re-purpose
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148 149 150 151 152 153 disp_ce_b <= 1’b1; dot_index <= 39; char_index <= 15; state <= state+1; disp_rs <= 1’b0; end // init for single char // start with MS char // Select the dot register 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 8’h06: begin // Load the user’s dot data into the dot reg, char by char disp_ce_b <= 1’b0; disp_data_out <= dots[dot_index]; // dot data from msb if (dot_index == 0) if (char_index == 0) state <= 5; // all done, latch data else begin char_index <= ch
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194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 always @(nibble) case (nibble) 4’h0: dots <= 4’h1: dots <= 4’h2: dots <= 4’h3: dots <= 4’h4: dots <= 4’h5: dots <= 4’h6: dots <= 4’h7: dots <= 4’h8: dots <= 4’h9: dots <= 4’hA: dots <= 4’hB: dots <= 4’hC: dots <= 4’hD: dots <= 4’hE: dots <= 4’hF: dots <= endcase 40’b00111110_01010001_01001001_01000101_00111110; 40’b00000000_01000010_01111111_01000000_00000000; 40’b01100010_01010001_01001001_01001001_01000110; 40’b00100010_01000001
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23 24 25 26 27 28 29 30 31 // horizontal: 800 pixels total // display 640 pixels per line reg hblank,vblank; wire hsyncon,hsyncoff,hreset,hblankon; assign hblankon = (hcount == VGA_HBLANKON); assign hsyncon = (hcount == VGA_HSYNCON); assign hsyncoff = (hcount == VGA_HSYNCOFF); assign hreset = (hcount == VGA_HRESET); 32 33 34 35 36 37 38 39 // vertical: 524 lines total // display 480 lines wire vsyncon,vsyncoff,vreset,vblankon; assign vblankon = hreset & (vcount == VGA_VBLANKON); assign vsyncon = hreset &
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10 11 12 13 14 15 16 module divider #(parameter WIDTH = 8) (input clk, sign, start, input [WIDTH-1:0] dividend, input [WIDTH-1:0] divider, output reg [WIDTH-1:0] quotient, output [WIDTH-1:0] remainder, output ready); 17 18 19 20 reg [WIDTH-1:0] quotient_temp; reg [WIDTH*2-1:0] dividend_copy, divider_copy, diff; reg negative_output; 21 22 23 assign remainder = (!negative_output) ? dividend_copy[WIDTH-1:0] : ~dividend_copy[WIDTH-1:0] + 1’b1; 24 25 26 27 reg [6:0] bit; reg del_ready = 1; assign ready =
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56 57 58 59 60 61 62 63 64 end quotient = (!negative_output) ? quotient_temp : ~quotient_temp + 1’b1; divider_copy = divider_copy >> 1; bit = bit - 1’b1; end end endmodule A.1.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ycrcb2rgb.
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35 36 37 38 39 40 41 begin const1 const2 const3 const4 const5 end = = = = = 10’b 10’b 10’b 10’b 10’b 0100101010; 0110011000; 0011010000; 0001100100; 1000000100; //1.164 //1.596 //0.813 //0.392 //2.017 = = = = = 01.00101010 01.10011000 00.11010000 00.01100100 10.
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81 82 83 84 85 86 87 88 89 90 91 92 /*always @ (posedge clk or posedge rst) if (rst) begin R_int <= 0; G_int <= 0; B_int <= end else begin X_int <= (const1 * (Y_reg - ’d64)) R_int <= X_int + (const2 * (Cr_reg G_int <= X_int - (const3 * (Cr_reg B_int <= X_int + (const5 * (Cb_reg end 0; ; - ’d512)); - ’d512)) - (const4 * (Cb_reg - ’d512)); - ’d512)); 93 94 95 96 97 98 */ /* limit assign R assign G assign B output to 0 = (R_int[20]) = (G_int[20]) = (B_int[20]) 4095, ? 0 : ? 0 : ? 0 : <0 equals o and >4
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24 25 reg reg old_frame; even_odd; // frames are even / odd interlaced // decode interlaced frame to this wire 26 27 28 wire wire frame = fvh[2]; frame_edge = frame & ~old_frame; 29 30 always @ (posedge vclk) begin//LLC1 is reference 31 old_dv <= dv; vwe <= dv && !fvh[2] & ~old_dv; // if data valid, write it 32 33 34 old_frame <= frame; even_odd = frame_edge ? ~even_odd : even_odd; 35 36 37 if (!fvh[2]) begin col <= fvh[0] ? (!fvh[2] row <= fvh[1] ? (!fvh[2] vdata <= (dv && end 38 39 40 41 42
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70 // compute address to store data in wire [9:0] y_addr = {y[1][8:0], eo[1]}; wire [9:0] x_addr = x[1]; 71 72 73 74 wire [7:0] R, G, B; ycrcb2rgb conv( R, G, B, clk, 1’b0, data[1][29:20], data[1][19:10], data[1][9:0] ); 75 76 77 78 wire [16:0] myaddr_o = (y_addr[7:0] << 8) + (y_addr[7:0] << 6) + x_addr[8:0]; wire [16:0] myaddr; synchronize #(.NSYNC(3), .
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19 // that are encoded within the stream, in YCrCb format. 20 21 // Make sure that the adv7185 is set to run in 16-bit LLC2 mode. 22 23 module ntsc_decode(clk, reset, tv_in_ycrcb, ycrcb, f, v, h, data_valid); 24 25 26 27 28 29 30 31 // // // // // // // clk - line-locked clock (in this case, LLC1 which runs at 27Mhz) reset - system reset tv_in_ycrcb - 10-bit input from chip.
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65 // in the sequence of pixels, it is looking. 66 67 68 // Once we determine where to start, the FSM goes through a normal // sequence of SAV process_YCrCb EAV... repeat 69 70 71 72 73 74 // The data stream looks as follows // SAV_FF | SAV_00 | SAV_00 | SAV_XY | Cb0 | Y0 | Cr1 | Y1 | Cb2 | Y2 | ... | EAV sequenc // There are two things we need to do: // 1. Find the two SAV blocks (stands for Start Active Video perhaps?) // 2.
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SAV_f2_cb0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y0; SAV_f2_y0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_cr1; SAV_f2_cr1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y1; SAV_f2_y1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_cb0; 111 112 113 114 115 // These states are here in the event that we want to cover these signals // in the future.
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157 158 159 160 161 y <= y_enable ? tv_in_ycrcb : y; cr <= cr_enable ? tv_in_ycrcb : cr; cb <= cb_enable ? tv_in_ycrcb : cb; f <= (current_state == SYNC_3) ? tv_in_ycrcb[8] : f; end 162 163 endmodule 164 165 166 167 168 169 170 171 172 173 174 /////////////////////////////////////////////////////////////////////////////// // // 6.
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203 204 205 /////////////////////////////////////////////////////////////////////////////// // Register 1 /////////////////////////////////////////////////////////////////////////////// 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 ‘define // 0: // 1: // 2: // 3: ‘define // 0: // 1: ‘define // 0: // 1: ‘define // 0: // 1: ‘define // 0: // 1: ‘define // 0: // 1: VIDEO_QUALITY 2’h0 Broadcast quality TV quality VCR quality Surveillance quality SQUARE_PIXEL_IN_MODE 1’b0
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249 ‘define ADV7185_REGISTER_2 {3’b000, ‘CORING, ‘Y_PEAKING_FILTER} 250 251 252 253 /////////////////////////////////////////////////////////////////////////////// // Register 3 /////////////////////////////////////////////////////////////////////////////// 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 ‘define INTERFACE_SELECT 2’h0 // 0: Philips-compatible // 1: Broktree API A-compatible // 2: Broktree API B-compatible // 3: [Not valid] ‘define OUTPUT_FORMAT 4’h0 /
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295 296 297 298 299 300 301 302 303 304 305 306 307 308 ‘define ‘define // 0: // 1: ‘define // 0: // 1: ‘define // 0: // 1: ‘define // 0: // 1: GENERAL_PURPOSE_OUTPUTS 4’b0000 GPO_0_1_ENABLE 1’b0 General purpose outputs 0 and 1 tristated General purpose outputs 0 and 1 enabled GPO_2_3_ENABLE 1’b0 General purpose outputs 2 and 3 tristated General purpose outputs 2 and 3 enabled BLANK_CHROMA_IN_VBI 1’b1 Chroma decoded and output during vertical blanking Chroma blanked during vertical blanking HLOCK_ENABLE 1
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341 342 ‘define INPUT_SATURATION_ADJUST 8’h8C 343 344 ‘define ADV7185_REGISTER_9 {‘INPUT_SATURATION_ADJUST} 345 346 347 348 /////////////////////////////////////////////////////////////////////////////// // Register A /////////////////////////////////////////////////////////////////////////////// 349 350 ‘define INPUT_BRIGHTNESS_ADJUST 8’h00 351 352 ‘define ADV7185_REGISTER_A {‘INPUT_BRIGHTNESS_ADJUST} 353 354 355 356 /////////////////////////////////////////////////////////////////////////////
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387 388 389 390 /////////////////////////////////////////////////////////////////////////////// // Register E /////////////////////////////////////////////////////////////////////////////// 391 392 393 394 395 396 397 398 399 400 401 ‘define TEMPORAL_DECIMATION_ENABLE // 0: Disable // 1: Enable ‘define TEMPORAL_DECIMATION_CONTROL // 0: Supress frames, start with even field // 1: Supress frames, start with odd field // 2: Supress even fields only // 3: Supress odd fields only ‘define TEMPORAL_DECIMATION_R
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433 ‘define ADV7185_REGISTER_F {‘RESET_CHIP, ‘TIMING_REACQUIRE, ‘POWER_DOWN_CHIP, ‘POWER_DOWN_LL 434 435 436 437 /////////////////////////////////////////////////////////////////////////////// // Register 33 /////////////////////////////////////////////////////////////////////////////// 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 ‘define PEAK_WHITE_UPDATE // 0: Update gain once per line // 1: Update gain once per field ‘define AVERAGE_BIRIGHTNESS_LINES // 0: Use lines 33 to
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479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ‘define ADV7185_REGISTER_24 ADV7185_REGISTER_25 ADV7185_REGISTER_26 ADV7185_REGISTER_27 ADV7185_REGISTER_28 ADV7185_REGISTER_29 ADV7185_REGISTER_2A ADV7185_REGISTER_2B ADV7185_REGISTER_2C ADV7185_REGISTER_2D ADV7185_REGISTER_2E ADV7185_REGIST
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525 526 527 528 529 530 531 532 533 534 535 536 537 538 $display(" $display(" $display(" $display(" $display(" $display(" $display(" $display(" $display(" $display(" $display(" $display(" $display(" end Register Register Register Register Register Register Register Register Register Register Register Register Register 3: 4: 5: 7: 8: 9: A: B: C: D: E: F: 33: 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", 0x%X", ‘ADV7185_REGISTER_3); ‘ADV7185_REGISTER_4); ‘ADV7185_REG
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571 assign reset_slow = reset_count != 0; 572 573 574 575 // // I2C driver // 576 577 578 579 reg load; reg [7:0] data; wire ack, idle; 580 581 582 583 i2c i2c(.reset(reset_slow), .clock4x(clock_slow), .data(data), .load(load), .ack(ack), .idle(idle), .scl(tv_in_i2c_clock), .
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617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 state <= state+1; end 8’h03: begin // Send ADV7185 address data <= 8’h8A; load <= 1’b1; if (ack) state <= state+1; end 8’h04: begin // Send subaddress of first register data <= 8’h00; if (ack) state <= state+1; end 8’h05: begin // Write to register 0 data <= ‘ADV7185_REGISTER_0 | {5’h00, {3{source}}}; if (ack) state <= state+
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663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 begin // Write to register 4 data <= ‘ADV7185_REGISTER_4; if (ack) state <= state+1; end 8’h0A: begin // Write to register 5 data <= ‘ADV7185_REGISTER_5; if (ack) state <= state+1; end 8’h0B: begin // Write to register 6 data <= 8’h00; // Reserved register, write all zeros if (ack) state <= state+1; end 8’h0C: begin // Write
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709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 end 8’h10: begin // Write to register B data <= ‘ADV7185_REGISTER_B; if (ack) state <= state+1; end 8’h11: begin // Write to register C data <= ‘ADV7185_REGISTER_C; if (ack) state <= state+1; end 8’h12: begin // Write to register D data <= ‘ADV7185_REGISTER_D; if (ack) state <= state+1; end 8’h13: begin // Write to register E
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755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 data <= 8’h8A; load <= 1’b1; if (ack) state <= state+1; end 8’h17: begin data <= 8’h33; if (ack) state <= state+1; end 8’h18: begin data <= ‘ADV7185_REGISTER_33; if (ack) state <= state+1; end 8’h19: begin load <= 1’b0; if (idle) state <= state+1; end 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 8’h1A: begin data <= 8’h8A; load <= 1’b1; if (ack) state <= state+1; end
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801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 if (ack) state <= state+1; end 8’h1E: begin data <= 8’hFF; if (ack) state <= state+1; end 8’h1F: begin load <= 1’b0; if (idle) state <= state+1; end 8’h20: begin // Idle if (old_source != source) state <= state+1; old_source <= source; end 8’h21: begin // Send ADV7185 address data <= 8’h8A; load <= 1’b1; if (ack) state <= state+1; end 8’
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847 // i2c module for use with the ADV7185 848 849 module i2c (reset, clock4x, data, load, idle, ack, scl, sda); 850 851 852 853 854 855 856 857 858 input reset; input clock4x; input [7:0] data; input load; output ack; output idle; output scl; output sda; 859 860 861 862 863 reg reg reg reg [7:0] ldata; ack, idle; scl; sdai; 864 865 reg [7:0] state; 866 867 assign sda = sdai ? 1’bZ : 1’b0; 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 alway
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893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 idle <= 1’b0; sdai <= 1’b0; state <= state+1; end 8’h02: begin scl <= 1’b0; state <= state+1; end 8’h03: // Send bit 7 begin ack <= 1’b0; sdai <= ldata[7]; state <= state+1; end 8’h04: begin scl <= 1’b1; state <= state+1; end 8’h05: begin state <= state+1; end 8’h06: begin scl <= 1’b0; state <= state+1; end 8’h07: begin sdai
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939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 state <= state+1; end 8’h0B: begin sdai <= ldata[5]; state <= state+1; end 8’h0C: begin scl <= 1’b1; state <= state+1; end 8’h0D: begin state <= state+1; end 8’h0E: begin scl <= 1’b0; state <= state+1; end 8’h0F: begin sdai <= ldata[4]; state <= state+1; end 8’h10: begin scl <= 1’b1; state <= state+1; end 8’h11: begin state <
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985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 begin scl <= 1’b1; state <= state+1; end 8’h15: begin state <= state+1; end 8’h16: begin scl <= 1’b0; state <= state+1; end 8’h17: begin sdai <= ldata[2]; state <= state+1; end 8’h18: begin scl <= 1’b1; state <= state+1; end 8’h19: begin state <= state+1; end 8’h1A: begin scl <= 1’b0; state <= s
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1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 8’h1E: begin scl <= 1’b0; state <= state+1; end 8’h1F: begin sdai <= ldata[0]; state <= state+1; end 8’h20: begin scl <= 1’b1; state <= state+1; end 8’h21: begin state <= state+1; end 8’h22: begin scl <= 1’b0; state <= state+1; end 8’h23: // Acknowledge bit begin state <= state+1;
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else state <= state+1; end 8’h27: begin sdai <= 1’b0; state <= state+1; end 8’h28: begin scl <= 1’b1; state <= state+1; end 8’h29: begin sdai <= 1’b1; state <= 0; end endcase 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 endmodule 1098 1099 A.1.9 1 2 3 4 flash int.
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21 22 23 24 25 26 27 28 reg reg reg reg reg reg reg [1:0] lop; [15:0] rdata; busy; [15:0] flash_wdata; flash_ddata; [23:0] flash_address; flash_oe_b, flash_we_b, flash_reset_b; 29 30 31 assign flash_ce_b = flash_oe_b && flash_we_b; assign flash_byte_b = 1; // 1 = 16-bit mode (A0 ignored) 32 33 assign flash_data = flash_ddata ? flash_wdata : 16’hZ; 34 35 36 initial flash_reset_b <= 1’b1; 37 38 reg [9:0] state; 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 alw
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67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 // // // // flash_ddata <= 0; flash_wdata <= wdata; lop <= op; if (op != ‘FLASHOP_IDLE) begin busy <= 1; state <= state+1; end else busy <= 0; end else if ((state==0) && flash_sts) busy <= 0; else if (state == 1) The first stage of a flash operation. The address bus is already set, so, if this is a read, we assert OE.
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busy <= 1; state <= state+1; 113 114 end 115 116 117 endmodule A.1.10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 flash manager.
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39 40 41 42 43 44 wire flash_busy; wire[15:0] fwdata; wire[15:0] frdata; wire[22:0] address; wire [1:0] op; //except these, which are internal to the interface 45 46 47 reg [1:0] mode; wire fsm_busy; 48 49 reg[2:0] state; //210 50 51 52 53 output[11:0] fsmstate; wire [7:0] fsmstateinv; assign fsmstate = {state,flash_busy,fsm_busy,fsmstateinv[4:0],mode}; //for de 54 55 56 57 58 //this guy flash_int flash(reset, clock, op, address, fwdata, frdata, flash_busy, flash_data, //and this test_fsm fsm (r
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busy <= 0; if(writemode) begin 85 86 87 busy <= 1; state <= MEM_INIT; 88 89 end 90 else 91 begin 92 busy <= 1; state <= READ_READY; 93 94 end 95 end 96 else 97 mode <= MODE_IDLE; 98 99 100 101 MEM_INIT://1 begin busy <= 1; mode <= MODE_INIT; if(fsm_busy) state <= MEM_WAIT; 102 103 104 105 end 106 107 108 109 110 MEM_WAIT://2 if(!fsm_busy) begin busy <= 0; state<= WRITE_READY; 111 112 end 113 else 114 mode <= MODE_IDLE; 115 116 117 118 119 WRITE_READY://3 if(dowrite) begin //
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busy <= 0; state <= WRITE_READY; 131 132 end 133 else 134 mode <= MODE_IDLE; 135 136 READ_READY://5 if(doread) begin 137 138 139 //ready to rea busy <= 1; mode <= MODE_READ; if(busy) state <= READ_WAIT; 140 141 142 143 //le end 144 else 145 busy <= 0; 146 147 READ_WAIT://6 if(!fsm_busy) begin 148 149 150 //waiting for flash to busy <= 0; state <= READ_READY; 151 152 end 153 else 154 mode <= MODE_IDLE; 155 156 default: begin state <= 3’d7; end 157 158 159 endcase 160 161 162
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12 13 ‘define STATUS_WRITE_ERROR ‘define STATUS_READ_WRONG_DATA 4’hB 4’hC 14 15 16 17 18 ‘define ‘define ‘define ‘define NUM_BLOCKS 128 BLOCK_SIZE 64*1024 LAST_BLOCK_ADDRESS ((‘NUM_BLOCKS-1)*‘BLOCK_SIZE) LAST_ADDRESS (‘NUM_BLOCKS*‘BLOCK_SIZE-1) 19 20 21 22 ‘define FLASHOP_IDLE 2’b00 ‘define FLASHOP_READ 2’b01 ‘define FLASHOP_WRITE 2’b10 23 24 25 26 27 28 29 30 31 32 33 34 35 36 module test_fsm (reset, clock, fop, faddress, fwdata, frdata, fbusy, dots, mode, busy, datai input reset, clock; output [1
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58 59 parameter MAX_ADDRESS = 23’h200000; 60 61 parameter HOME = 8’h12; 62 63 64 65 66 67 68 69 70 71 72 73 74 always @(posedge clock) if (reset) begin state <= HOME; status <= ‘STATUS_RESET; faddress <= 0; fop <= ‘FLASHOP_IDLE; busy <= 1; end else if (!fbusy && (fop == ‘FLASHOP_IDLE)) case (state) 75 76 77 78 79 80 81 HOME://12 case(mode) MODE_INIT: begin state <= 8’h00; busy <= 1; end 82 MODE_WRITE: begin state <= 8’h0C; busy <= 1; end 83 84 85 86 87 MODE_READ: begin busy <= 1; if(status == ‘ST
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104 105 106 107 108 109 110 111 112 113 ////////////////////////////////////////////////////////////////////// 8’h00: begin // Issue "read id codes" command status <= ‘STATUS_READ_ID; faddress <= 0; fwdata <= 16’h0090; fop <= ‘FLASHOP_WRITE; state <= state+1; end 114 115 116 117 118 119 120 121 8’h01: begin // Read manufacturer code faddress <= 0; fop <= ‘FLASHOP_READ; state <= state+1; end 122 123 124 125 126 127 128 129 130 131 132 8’h02: if (frdata != 16’h0089) // 16’h0089 = Intel status <= ‘STATUS_
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150 151 152 153 fwdata <= 16’h60; fop <= ‘FLASHOP_WRITE; state <= state+1; end 154 155 156 157 158 159 160 161 162 8’h05: begin // Issue "confirm clear lock bits" command faddress <= 0; fwdata <= 16’hD0; fop <= ‘FLASHOP_WRITE; state <= state+1; end 163 164 165 166 167 168 169 170 8’h06: begin // Read status faddress <= 0; fop <= ‘FLASHOP_READ; state <= state+1; end 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 8’h07: if (frdata[7] == 1) // Done clearing lock bits if (frdata[6:1] ==
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196 197 state <= state+1; end 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 8’h09: begin fwdata <= 16’hD0; // Issue "confirm erase" command fop <= ‘FLASHOP_WRITE; state <= state+1; end 8’h0A: begin fop <= ‘FLASHOP_READ; state <= state+1; end 8’h0B: if (frdata[7] == 1) // Done erasing block if (frdata[6:1] == 0) // No errors if (faddress != MAX_ADDRESS) // ‘LAST_BLOCK_ADDRESS) begin faddress <= faddress+‘BLOCK_SIZE; fop <= ‘FLAS
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242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 8’h0D: begin fwdata <= data_to_store; // Finish write fop <= ‘FLASHOP_WRITE; state <= state+1; end 8’h0E: begin // Read status register fop <= ‘FLASHOP_READ; state <= state+1; end 8’h0F: if (frdata[7] == 1) // Done writing if (frdata[6:1] == 0) // No errors if (faddress != 23’h7FFFFF) // ‘LAST_ADDRESS) begin faddress <= faddress+1; fop <= ‘FLASHOP_IDLE; state <= HOME; end else status <= ‘STATUS_WRITE
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288 289 290 fop <= ‘FLASHOP_READ; state <= HOME; end 291 292 293 default: begin status <= ‘STATUS_BAD_MANUFACTURER; faddress <= 0; state <= HOME; 294 295 296 297 end 298 299 300 301 endcase else fop <= ‘FLASHOP_IDLE; 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 function [39:0] nib2char; input [3:0] nib; begin case (nib) 4’h0: nib2char = 40’b00111110_01010001_01001001_01000101_00111110; 4’h1: nib2char = 40’b00000000_01000010_01111111_01000000_000000
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334 335 336 337 nib2char(faddress[15:12]), nib2char(faddress[11:8]), nib2char(faddress[7:4]), nib2char(faddress[3:0])}; 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 always @(status or address_dots or data_dots) case (status) ‘STATUS_RESET: dots <= {40’b01111111_00001001_00011001_00101001_01000110, // 40’b01111111_01001001_01001001_01001001_01000001, // 40’b00100110_01001001_01001001_
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380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 40’b00000000_00000000_00000000_00000000_00000000, address_dots}; ‘STATUS_ERASING: dots <= {40’b01111111_01001001_01001001_01001001_01000001, 40’b01111111_00001001_00011001_00101001_01000110, 40’b01111110_00001001_00001001_00001001_01111110, 40’b00100110_01001001_01001001_01001001_00110010, 40’b00000000_01000001_01111111_01000
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426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 40’b00100110_01001001_01001001_01001001_00110010, // 40’b00100110_01001001_01001001_01001001_00110010, // 40’b01111111_01001001_01001001_01001001_01000001, // 40’b01111111_01000001_01000001_01000001_00111110, // 40’b00000000_00000000_00000000_00000000_00000000, // 40’b00101010_00011100_01111111_00011100_00101010, // 40’b00101
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472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 40’b01111111_00001000_00010100_00100010_01000001, // K 40’b00100110_01001001_01001001_01001001_00110010, // S 40’b00000000_00000000_00000000_00000000_00000000, 40’b00000000_00000000_00000000_00000000_00000000, data_dots}; ‘STATUS_ERASE_BLOCK_ERROR: dots <= {40’b01111111_01001001_01001001_01001001_01000001, // E 40’b01111111_00001
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518 endmodule A.1.12 1 2 3 4 5 6 7 usb input.
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rd <= 1; state <= WAIT; 43 44 end 45 46 47 48 //we can’t read data else if(~hold) begin newout <= 0; case(state) WAIT: if(~rxf) begin 49 50 51 52 53 //if rxf is low and rd <= 1; state <= WAIT2; 54 55 //and end 56 57 WAIT2: 58 if(~rxf) begin 59 60 //double check rd <= 1; state <= WAIT3; 61 62 end 63 else 64 state <= WAIT; 65 66 WAIT3: 67 if(~rxf) begin 68 69 //and triple check ( rd <= 0; state <= DATA_COMING; 70 71 end 72 else 73 state <= WAIT; 74 75 DATA_COMING: //once rd
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newout <= 1; 89 //let folks know end 90 91 DATA_LEAVING: begin 92 93 //wait a cycle //rd <= 1; // ORIGINAL state <= DATA_LEAVING_2; newout <= 0; //let folks know 94 95 96 end 97 98 DATA_LEAVING_2: //wait another cycle state <= DATA_LEAVING_3; 99 100 101 DATA_LEAVING_3: //wait another cycle state <= DATA_LEAVING_4; 102 103 104 DATA_LEAVING_4: //wait another cycle state <= DATA_LEAVING_5; 105 106 107 DATA_LEAVING_5: //wait another cycle state <= DATA_LEAVING_6; 108 109 110 DATA_LEAVING_6:
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12 13 14 15 Script runs through a coe file (basically row after row of 8 bit values) and sends line by line. ’’’ 16 17 ser = serial.Serial(port=’/dev/tty.usbserial-FTDHKA57’) 18 19 a = open(’audio_convert/Fa48k8bit.coe’,’r’) 20 21 for line in a: 22 line = line.rstrip()[0:-1] line = int(line, base=2) 23 24 25 b = struct.pack("
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23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 // CHANGES FOR BOARD REVISION 003 // // 1) Combined flash chip enables into a single signal, flash_ce_b. // // CHANGES FOR BOARD REVISION 002 // // 1) Added SRAM clock feedback path input and output // 2) Renamed "mousedata" to "mouse_data" // 3) Renamed some ZBT memory signals.
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69 70 71 vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync, 72 73 74 75 tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset, 76 77 78 79 80 tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff, tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
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115 analyzer1_data, analyzer1_clock, analyzer2_data, analyzer2_clock, analyzer3_data, analyzer3_clock, analyzer4_data, analyzer4_clock); 116 117 118 119 120 121 122 output beep, audio_reset_b, ac97_synch, ac97_sdata_out; input ac97_bit_clock, ac97_sdata_in; 123 124 125 126 output [7:0] vga_out_red, vga_out_green, vga_out_blue; output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync; 127 128 129 130 131 output [9:0] tv_out_ycrcb; output tv_out_reset_b, tv_out_clock, t
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161 input mouse_clock, mouse_data, keyboard_clock, keyboard_data; input clock_27mhz, clock1, clock2; 162 163 164 165 166 167 output input output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b; disp_data_in; disp_data_out; 168 169 170 171 172 input button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up; input [7:0] switch; output [7:0] led; 173 174 inout [31:0] user1, user2, user3, user4; 175 176 inout [43:0] daughtercard; 177 178 179 180 1
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207 208 209 210 assign assign assign assign tv_out_hsync_b = 1’b1; tv_out_vsync_b = 1’b1; tv_out_blank_b = 1’b1; tv_out_subcar_reset = 1’b0; 211 212 213 214 215 216 217 218 219 220 221 // Video Input //assign tv_in_i2c_clock = 1’b0; assign tv_in_fifo_read = 1’b1; assign tv_in_fifo_clock = 1’b0; assign tv_in_iso = 1’b1; //assign tv_in_reset_b = 1’b0; assign tv_in_clock = clock_27mhz;//1’b0; //assign tv_in_i2c_data = 1’bZ; // tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, // tv_in_ae
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253 // // flash_sts is an input 254 255 256 257 258 // RS-232 Interface assign rs232_txd = 1’b1; assign rs232_rts = 1’b1; // rs232_rxd and rs232_cts are inputs 259 260 261 // PS/2 Ports // mouse_clock, mouse_data, keyboard_clock, and keyboard_data are inputs 262 263 264 265 266 267 // Buttons, Switches, and Individual LEDs //assign led = 8’hFF; // button0, button1, button2, button3, button_enter, button_right, // button_left, button_down, button_up, and switches are inputs 268 269 270 271 272 273 /
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299 300 301 302 303 304 305 306 307 308 // // A shift register primitive is used to generate an active-high reset // signal that remains high for 16 clock cycles after configuration finishes // and the FPGA’s internal clocks begin toggling. // //////////////////////////////////////////////////////////////////////////// wire reset; SRL16 reset_sr(.D(1’b0), .CLK(clock_27mhz), .Q(reset), .A0(1’b1), .A1(1’b1), .A2(1’b1), .A3(1’b1)); defparam reset_sr.
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345 346 347 348 349 350 351 352 353 354 355 //////////////////////////////////////////////////////////////////////////////////////////// wire btn_up_clean, btn_down_clean, btn_left_clean, btn_right_clean; wire btn_up_sw, btn_down_sw, btn_left_sw, btn_right_sw; debounce btn_up_debounce(.reset(reset), .clock(clock_27mhz), .noisy(button_up), .clean(btn_u debounce btn_down_debounce(.reset(reset), .clock(clock_27mhz), .noisy(button_down), .clean(b debounce btn_left_debounce(.reset(reset), .clock(clock_27mhz), .
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391 392 393 394 395 396 397 398 399 //////////////////////////////////////////////////////////////////////////////////////////// wire acc_ready; wire signed [15:0] acc_x; wire signed [15:0] acc_y; reg signed [15:0] acc_x_reg; reg signed [15:0] acc_y_reg; acc a(.clk(sys_clk), .sdo(user1[0]), .reset(reset), .ncs(user1[1]), .sda(user1[2]), .scl(user1[3]), .ready(acc_ready), .x(acc_x), .
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437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 assign y1_raw = quad_corners[65:57]; assign x1_raw = quad_corners[75:66]; move_cursor move_cursor(.clk(vsync), .up(btn_up_sw & ~old_btn_up), .down(btn_down_sw & ~old_btn_down), .left(btn_left_sw & ~old_btn_left), .right(btn_right_sw & ~old_btn_right), .override(override_sw), .switch(quad_corner_sw), .x1_raw(x1_raw), .y1_raw(y1_raw), .x2_raw(x2_raw), .y2_raw(y2_raw), .x3_raw(x3_raw), .
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483 484 485 486 487 488 489 490 491 492 493 494 495 //////////////////////////////////////////////////////////////////////////////////////////// wire signed[67:0] p1_inv; wire signed[68:0] p2_inv; wire signed[78:0] p3_inv; wire signed[67:0] p4_inv; wire signed[68:0] p5_inv; wire signed[78:0] p6_inv; wire signed[58:0] p7_inv; wire signed[59:0] p8_inv; wire signed[70:0] p9_inv; wire signed[78:0] dec_numx_horiz; wire signed[78:0] dec_numy_horiz; wire signed[70:0] dec_denom_horiz; 496 497 498 499 500 501 502
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529 530 531 532 533 534 535 536 wire[16:0] vga_out_addr; wire[11:0] ntsc_cb_din; wire[11:0] ntsc_dout; wire[11:0] vga_din; wire[11:0] vga_dout; wire ntsc_cb_in_wr; wire vga_in_wr; assign ntsc_cb_in_wr = 1; 537 538 // ntsc 539 540 541 542 543 adv7185init adv7185(.reset(reset), .clock_27mhz(clock_27mhz), .source(1’b0), .tv_in_reset_b(tv_in_reset_b), .tv_in_i2c_clock(tv_in_i2c_clock), .
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cur_y <= cur_y + 1; 575 end 576 577 end 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 // instantiate the pixel_map module pixel_map pixel_map(.clk(sys_clk), .p1_inv(p1_inv), .p2_inv(p2_inv), .p3_inv(p3_inv), .p4_inv(p4_inv), .p5_inv(p5_inv), .p6_inv(p6_inv), .p7_inv(p7_inv), .p8_inv(p8_inv), .p9_inv(p9_inv), .dec_numx_horiz(dec_numx_horiz), .dec_numy_horiz(dec_numy_horiz), .dec_denom_horiz(dec_denom_horiz), .pixel_in(ntsc_dout), .pixel_out(vga_din), .
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.a_addr(vga_in_addr), .a_din(vga_din), .b_clk(vga_clk), .b_addr(vga_out_addr), .
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667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 // allow user to adjust volume wire vup,vdown; reg old_vup,old_vdown; debounce bup(.reset(reset),.clock(clock_27mhz),.noisy(~button3),.clean(vup)); debounce bdown(.reset(reset),.clock(clock_27mhz),.noisy(~button_down),.
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.audioTrigger(audioTrigger), 713 714 // AC97 I/O .ready(ready), .from_ac97_data(from_ac97_data), .to_ac97_data(to_ac97_data), 715 716 717 718 719 // Flash I/O .flash_data(flash_data), .flash_address(flash_address), .flash_ce_b(flash_ce_b), .flash_oe_b(flash_oe_b), .flash_we_b(flash_we_b), .flash_reset_b(flash_reset_b), .flash_byte_b(flash_byte_b), .flash_sts(flash_sts), .busy(busy), 720 721 722 723 724 725 726 727 728 729 730 // USB I/O .data(user1[31:24]), //the data pins from the USB fifo .
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19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 # 5) Reversed disp_data_in and disp_data_out signals, so that "out" is an # output of the FPGA, and "in" is an input. # # CHANGES FOR BOARD REVISION 003 # # 1) Combined flash chip enables into a single signal, flash_ce_b. # 2) Moved SRAM feedback clock loop to FPGA pins AL28 (out) and AJ16 (in). # 3) Moved rs232_rts to FPGA pin R3. # 4) Moved flash_address<1> to AE14.
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65 66 67 68 NET NET NET NET "ac97_sdata_out" "ac97_sdata_in" "ac97_synch" "ac97_bit_clock" LOC="ac18" | IOSTANDARD=LVDCI_33; LOC="aj24"; LOC="ac17" | IOSTANDARD=LVDCI_33; LOC="ah24"; 69 70 71 NET "sys_clk" TNM_NET = sys_clk; TIMESPEC TS_sys_clk = PERIOD "sys_clk" 20 ns HIGH 50%; 72 73 74 75 76 77 NET "vga_clk" TNM_NET = vga_clk; TIMESPEC TS_vga_clk = PERIOD "vga_clk" 40 ns HIGH 50%; # # VGA Output # 78 79 80 81 82 83 84 85 86 NET NET NET NET NET NET NET NET "vga_out_red<7>" "vga_out_red<6>" "vga_o
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111 112 113 114 # # Video Output # 115 116 117 118 119 120 121 122 123 124 125 NET NET NET NET NET NET NET NET NET NET "tv_out_ycrcb<9>" "tv_out_ycrcb<8>" "tv_out_ycrcb<7>" "tv_out_ycrcb<6>" "tv_out_ycrcb<5>" "tv_out_ycrcb<4>" "tv_out_ycrcb<3>" "tv_out_ycrcb<2>" "tv_out_ycrcb<1>" "tv_out_ycrcb<0>" LOC="p27" LOC="r27" LOC="t29" LOC="h26" LOC="j26" LOC="l26" LOC="m26" LOC="n26" LOC="p26" LOC="r26" | | | | | | | | | | IOSTANDARD=LVDCI_33; IOSTANDARD=LVDCI_33; IOSTANDARD=LVDCI_33; IOSTANDARD=LVDCI_33; IO
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157 158 159 160 NET NET NET NET "tv_in_ycrcb<3>" "tv_in_ycrcb<2>" "tv_in_ycrcb<1>" "tv_in_ycrcb<0>" LOC="r25"; LOC="l30"; LOC="m31"; LOC="m30"; NET NET NET NET NET NET NET NET NET NET NET NET NET "tv_in_data_valid" LOC="ah25"; "tv_in_line_clock1" LOC="ad16" | IOSTANDARD=LVDCI_33; "tv_in_line_clock2" LOC="ad17" | IOSTANDARD=LVDCI_33; "tv_in_aef" LOC="aj23"; "tv_in_hff" LOC="ah23"; "tv_in_aff" LOC="aj22"; "tv_in_i2c_clock" LOC="ad21" | IOSTANDARD=LVDCI_33; "tv_in_i2c_data" LOC="ad19" | IOSTANDARD=LVDCI_3
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203 204 205 206 207 208 209 210 211 212 213 214 215 NET NET NET NET NET NET NET NET NET NET NET NET NET "ram0_data<12>" "ram0_data<11>" "ram0_data<10>" "ram0_data<9>" "ram0_data<8>" "ram0_data<7>" "ram0_data<6>" "ram0_data<5>" "ram0_data<4>" "ram0_data<3>" "ram0_data<2>" "ram0_data<1>" "ram0_data<0>" LOC="w28" LOC="v28" LOC="u29" LOC="u28" LOC="aa27" LOC="ad31" LOC="ac30" LOC="ac31" LOC="ab30" LOC="ab31" LOC="aa30" LOC="aa31" LOC="y30" | | | | | | | | | | | | | IOSTANDARD=LVDCI_33 IOSTANDARD=LVDCI_33 I
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249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "ram1_data<34>" "ram1_data<33>" "ram1_data<32>" "ram1_data<31>" "ram1_data<30>" "ram1_data<29>" "ram1_data<28>" "ram1_data<27>" "ram1_data<26>" "ram1_data<25>" "ram1_data<24>" "ram1_data<23>" "ram1_data<22>" "ram1_data<21>" "ram1_
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295 296 297 298 299 300 301 302 303 NET NET NET NET NET NET NET NET NET "ram1_address<8>" "ram1_address<7>" "ram1_address<6>" "ram1_address<5>" "ram1_address<4>" "ram1_address<3>" "ram1_address<2>" "ram1_address<1>" "ram1_address<0>" LOC="ad4" | IOSTANDARD=LVDCI_33; LOC="u3" | IOSTANDARD=LVDCI_33; LOC="w4" | IOSTANDARD=LVDCI_33; LOC="ac8" | IOSTANDARD=LVDCI_33; LOC="ab8" | IOSTANDARD=LVDCI_33; LOC="aa8" | IOSTANDARD=LVDCI_33; LOC="y7" | IOSTANDARD=LVDCI_33; LOC="y8" | IOSTANDARD=LVDCI_33; LOC="ad7" | IOS
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341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "flash_address<23>" "flash_address<22>" "flash_address<21>" "flash_address<20>" "flash_address<19>" "flash_address<18>" "flash_address<17>" "flash_address<16>" "flash_address<15>" "flash_address<14>" "flash_address<13>" "flash_address<12>" "flash_address<11>" "flash_address<10>" "flash_address<9>" "flash_address<8>"
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387 388 389 390 NET NET NET NET "mouse_clock" LOC="ac16"; "mouse_data" LOC="ac15"; "keyboard_clock" LOC="ag16"; "keyboard_data" LOC="af16"; 391 392 393 394 # # Clocks # 395 396 397 398 NET "clock_27mhz" LOC="c16"; NET "clock1" LOC="h16"; NET "clock2" LOC="c15"; 399 400 401 402 # # Alphanumeric Display # 403 404 405 406 407 408 409 410 NET NET NET NET NET NET NET "disp_blank" LOC="af12" | IOSTANDARD=LVDCI_33; "disp_data_in" LOC="ae12"; "disp_clock" LOC="af14" | IOSTANDARD=LVDCI_33; "disp_rs" LOC="
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433 NET "switch<0>" LOC="ak26"; 434 435 436 437 # # Discrete LEDs # 438 439 440 441 442 443 444 445 446 NET NET NET NET NET NET NET NET "led<7>" "led<6>" "led<5>" "led<4>" "led<3>" "led<2>" "led<1>" "led<0>" LOC="ae17" LOC="af17" LOC="af18" LOC="af19" LOC="af20" LOC="ag21" LOC="ae21" LOC="ae22" | | | | | | | | IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; 447 448 449 450 451 # # User Pins # 452 453
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479 480 481 482 483 484 NET NET NET NET NET NET "user1<5>" "user1<4>" "user1<3>" "user1<2>" "user1<1>" "user1<0>" LOC="a9" LOC="a8" LOC="b6" LOC="b5" LOC="c5" LOC="b3" | | | | | | IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "user2<31>" LOC="b27" | IOSTANDARD=LVTTL; "user2<30>" LOC="b26" | IOSTANDARD=LVTTL; "user
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525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "user3<26>" LOC="f11" | IOSTANDARD=LVTTL; "user3<25>" LOC="g10" | IOSTANDARD=LVTTL; "user3<24>" LOC="h10" | IOSTANDARD=LVTTL; "user3<23>" LOC="a15" | IOSTANDARD=LVTTL; "user3<22>" LOC="a14" | IOSTANDARD=LVTTL; "user3<21>" LOC="e15" | IOSTANDARD=LVTTL; "user3<20>" LOC="e14" | IOSTANDARD=LVTTL;
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571 572 573 574 575 576 577 578 579 580 581 582 583 584 NET NET NET NET NET NET NET NET NET NET NET NET NET NET "user4<13>" LOC="e23" | IOSTANDARD=LVTTL; "user4<12>" LOC="e21" | IOSTANDARD=LVTTL; "user4<11>" LOC="e19" | IOSTANDARD=LVTTL; "user4<10>" LOC="e17" | IOSTANDARD=LVTTL; "user4<9>" LOC="b19" | IOSTANDARD=LVTTL; "user4<8>" LOC="b18" | IOSTANDARD=LVTTL; "user4<7>" LOC="h23" | IOSTANDARD=LVTTL; "user4<6>" LOC="g23" | IOSTANDARD=LVTTL; "user4<5>" LOC="g21" | IOSTANDARD=LVTTL; "user4<4>" LOC="f20" | IO
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617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "daughtercard<16>" LOC="G4" | IOSTANDARD=LVTTL; "daughtercard<15>" LOC="H4" | IOSTANDARD=LVTTL; "daughtercard<14>" LOC="J3" | IOSTANDARD=LVTTL; "daughtercard<13>" LOC="J4" | IOSTANDARD=LVTTL; "daughtercard<12>" LOC="D2" | IOSTANDARD=LVTTL; "daughtercard<11>" LOC="D1" | IOSTANDARD=LVTTL; "daughtercard<10>" LOC="E2" | IOSTANDARD=LVTTL; "daughtercard<9>" LOC="E1" | IOSTANDAR
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663 664 665 666 667 668 NET NET NET NET NET "systemace_ce_b" LOC="E28" | IOSTANDARD=LVTTL; "systemace_we_b" LOC="P31" | IOSTANDARD=LVTTL; "systemace_oe_b" LOC="R31" | IOSTANDARD=LVTTL; "systemace_irq" LOC="D29"; "systemace_mpbrdy" LOC="L31"; 669 670 671 672 # # Logic Analyzer # 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "analyzer1_data<15>" LOC="G1" | IOSTANDARD=LVTTL; "analyzer1_data<14>" LOC="H3" | IOST
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709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "analyzer3_data<15>" LOC="k24" | IOSTANDARD=LVTTL; "analyzer3_data<14>" LOC="k25" | IOSTANDARD=LVTTL; "analyzer3_data<13>" LOC="k22" | IOSTANDARD=LVTTL; "analyzer3_data<12>" LOC="l24" | IOSTANDARD=LVTTL; "analyzer3_data<11>" LOC="l25" | IOSTANDARD=LVTTL; "analyzer3_data<10>" LOC="l22" | IOSTANDARD=LVTTL; "analyzer3_data<9>" LOC="l23" | IOSTANDARD=LVTTL; "analyzer3_dat
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6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 // Create Date: 16:26:11 11/16/2014 // Design Name: // Module Name: acc // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.
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52 53 output[W-1:0] par); reg[W-2:0] par_reg = 0; 54 55 56 57 always @(posedge clk) begin par_reg <= {par_reg[W-3:0], ser}; end 58 59 60 assign par = {par_reg, ser}; endmodule 61 62 63 64 65 66 /* reduces the system clock by a factor of 6 */ module acc_clk(input clk /* system clock */ , output dev_clk); parameter TICKS = 9; 67 68 69 reg [3:0] count = 0; reg sig_reg = 0; 70 71 72 73 74 75 76 77 78 79 80 81 82 always @(posedge clk) begin if (count == TICKS) begin // flip at half period sig_reg <= ~
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98 99 100 reg signed [15:0] accum = 0; reg [5:0] num_samples = 0; reg signed [15:0] data_right_shift; 101 102 103 104 105 always @(*) begin data_right_shift = {data[15], data[15], data[15], data[15], data[15], data[15:5]}; end 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 always @(posedge clock) begin if (reset) begin accum <= 0; num_samples <= 0; offset <= 0; end else if (in_ready) begin num_samples <= (num_samples == 6’d32) ? num_samples : num_samples + samples[offset] <
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144 145 reg ncs_reg; 146 147 148 wire dev_clk; acc_clk ac(.clk(clk), .dev_clk(dev_clk)); 149 150 151 152 reg[7:0] par_in; reg pts_start; par_to_ser pts(.clk(dev_clk), .par(par_in), .start(pts_start), .ser(sda)); 153 154 155 wire[7:0] par_out; ser_to_par stp(.clk(dev_clk), .ser(sdo), .par(par_out)); 156 157 158 159 160 161 162 163 164 165 166 167 reg ma_x_in_ready; reg [7:0] x_low_bits = 0; reg signed [15:0] ma_x_in; wire ma_x_avg_ready; wire signed [15:0] ma_x_avg; moving_avg ma_x( .
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count <= count + 1; 190 end 191 end X_READ: begin if (count == 5’d25) begin count <= 0; state <= Y_READ; end else begin count <= count + 1; end if (count == 5’d17) begin x_low_bits <= par_out; end end Y_READ: begin if (count == 5’d25) begin count <= 0; state <= X_READ; end else begin count <= count + 1; end if (count == 5’d17) begin y_low_bits <= par_out; end end 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 endcase 217 218 end 219 220 221 222 2
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end X_READ: begin pts_start = (count == 5’d1) ? 1 : 0; par_in = (count == 5’d1) ? 8’hF2 : 0; // 1 for R, 1 for MB ma_x_in_ready = (count == 5’d25) ? 1 : 0; ma_x_in = (count == 5’d25) ? {par_out, x_low_bits} : 0; ma_y_in_ready = 0; ma_y_in = 0; ncs_reg = (count == 5’d25) ? 1 : 0; end Y_READ: begin pts_start = (count == 5’d1) ? 1 : 0; par_in = (count == 5’d1) ? 8’hF4 : 0; // 1 for R, 1 for MB ma_y_in_ready = (count == 5’d25) ? 1 : 0; ma_y_in = (count == 5’d25) ? {par_out, y_low_bits} : 0; ma_x_in_ready = 0; m
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16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 12’d4: quad_corners = 76’d166903815503556664320; 12’d5: quad_corners = 76’d166903815503556664320; 12’d6: quad_corners = 76’d166903815503556664320; 12’d7: quad_corners = 76’d166903815503556664320; 12’d8: quad_corners = 76’d166903815503556664320; 12’d9: quad_corners = 76’d166903815503556664320; 12’d10: quad_corners = 76’d166903815503556664320; 12’d11: quad_corners = 76’d16
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62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 12’d50: 12’d51: 12’d52: 12’d53: 12’d54: 12’d55: 12’d56: 12’d57: 12’d58: 12’d59: 12’d60: 12’d61: 12’d62: 12’d63: 12’d64: 12’d65: 12’d66: 12’d67: 12’d68: 12’d69: 12’d70: 12’d71: 12’d72: 12’d73: 12’d74: 12’d75: 12’d76: 12’d77: 12’d78: 12’d79: 12’d80: 12’d81: 12’d82: 12’d83: 12’d84: 12’d85: 12’d86: 12’d87: 12’d88: 12’d89: 12’d90: 12’d91: 12’d92: 12’d93: 12’d94: 12’d9
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108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 12’d96: quad_corners = 76’d165458581135586242565; 12’d97: quad_corners = 76’d165313902172117936646; 12’d98: quad_corners = 76’d165169223208381195272; 12’d99: quad_corners = 76’d238811520539482660361; 12’d100: quad_corners = 76’d238666841575745918475; 12’d101: quad_corners = 76’d312165023443625184781; 12’d102: quad_corners = 7
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154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 12’d142: 12’d143: 12’d144: 12’d145: 12’d146: 12’d147: 12’d148: 12’d149: 12’d150: 12’d151: 12’d152: 12’d153: 12’d154: 12’d155: 12’d156: 12’d157: 12’d158: 12’d159: 12’d160: 12’d161: 12’d162: 12’d163: 12’d164: 12’d165: 12’d166: 12’d167: 12’d168: 12’d169: 12’d170: 12’d171: 12’d172: 12’d173: 12’d174: 12’d175: 12’d176: 12’d177: 12’
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200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 12’d188: 12’d189: 12’d190: 12’d191: 12’d192: 12’d193: 12’d194: 12’d195: 12’d196: 12’d197: 12’d198: 12’d199: 12’d200: 12’d201: 12’d202: 12’d203: 12’d204: 12’d205: 12’d206: 12’d207: 12’d208: 12’d209: 12’d210: 12’d211: 12’d212: 12’d213: 12’d214: 12’d215: 12’d216: 12’d217: 12’d218: 12’d219: 12’d220: 12’d221: 12’d222: 12’d223: 12’
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246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 12’d234: 12’d235: 12’d236: 12’d237: 12’d238: 12’d239: 12’d240: 12’d241: 12’d242: 12’d243: 12’d244: 12’d245: 12’d246: 12’d247: 12’d248: 12’d249: 12’d250: 12’d251: 12’d252: 12’d253: 12’d254: 12’d255: 12’d256: 12’d257: 12’d258: 12’d259: 12’d260: 12’d261: 12’d262: 12’d263: 12’d264: 12’d265: 12’d266: 12’d267: 12’d268: 12’d269: 12’
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292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 12’d280: 12’d281: 12’d282: 12’d283: 12’d284: 12’d285: 12’d286: 12’d287: 12’d288: 12’d289: 12’d290: 12’d291: 12’d292: 12’d293: 12’d294: 12’d295: 12’d296: 12’d297: 12’d298: 12’d299: 12’d300: 12’d301: 12’d302: 12’d303: 12’d304: 12’d305: 12’d306: 12’d307: 12’d308: 12’d309: 12’d310: 12’d311: 12’d312: 12’d313: 12’d314: 12’d315: 12’
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338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 12’d326: 12’d327: 12’d328: 12’d329: 12’d330: 12’d331: 12’d332: 12’d333: 12’d334: 12’d335: 12’d336: 12’d337: 12’d338: 12’d339: 12’d340: 12’d341: 12’d342: 12’d343: 12’d344: 12’d345: 12’d346: 12’d347: 12’d348: 12’d349: 12’d350: 12’d351: 12’d352: 12’d353: 12’d354: 12’d355: 12’d356: 12’d357: 12’d358: 12’d359: 12’d360: 12’d361: 12’
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384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 12’d372: 12’d373: 12’d374: 12’d375: 12’d376: 12’d377: 12’d378: 12’d379: 12’d380: 12’d381: 12’d382: 12’d383: 12’d384: 12’d385: 12’d386: 12’d387: 12’d388: 12’d389: 12’d390: 12’d391: 12’d392: 12’d393: 12’d394: 12’d395: 12’d396: 12’d397: 12’d398: 12’d399: 12’d400: 12’d401: 12’d402: 12’d403: 12’d404: 12’d405: 12’d406: 12’d407: 12’
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430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 12’d418: 12’d419: 12’d420: 12’d421: 12’d422: 12’d423: 12’d424: 12’d425: 12’d426: 12’d427: 12’d428: 12’d429: 12’d430: 12’d431: 12’d432: 12’d433: 12’d434: 12’d435: 12’d436: 12’d437: 12’d438: 12’d439: 12’d440: 12’d441: 12’d442: 12’d443: 12’d444: 12’d445: 12’d446: 12’d447: 12’d448: 12’d449: 12’d450: 12’d451: 12’d452: 12’d453: 12’
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476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 12’d464: 12’d465: 12’d466: 12’d467: 12’d468: 12’d469: 12’d470: 12’d471: 12’d472: 12’d473: 12’d474: 12’d475: 12’d476: 12’d477: 12’d478: 12’d479: 12’d480: 12’d481: 12’d482: 12’d483: 12’d484: 12’d485: 12’d486: 12’d487: 12’d488: 12’d489: 12’d490: 12’d491: 12’d492: 12’d493: 12’d494: 12’d495: 12’d496: 12’d497: 12’d498: 12’d499: 12’
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522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 12’d510: 12’d511: 12’d512: 12’d513: 12’d514: 12’d515: 12’d516: 12’d517: 12’d518: 12’d519: 12’d520: 12’d521: 12’d522: 12’d523: 12’d524: 12’d525: 12’d526: 12’d527: 12’d528: 12’d529: 12’d530: 12’d531: 12’d532: 12’d533: 12’d534: 12’d535: 12’d536: 12’d537: 12’d538: 12’d539: 12’d540: 12’d541: 12’d542: 12’d543: 12’d544: 12’d545: 12’
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568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 12’d556: 12’d557: 12’d558: 12’d559: 12’d560: 12’d561: 12’d562: 12’d563: 12’d564: 12’d565: 12’d566: 12’d567: 12’d568: 12’d569: 12’d570: 12’d571: 12’d572: 12’d573: 12’d574: 12’d575: 12’d576: 12’d577: 12’d578: 12’d579: 12’d580: 12’d581: 12’d582: 12’d583: 12’d584: 12’d585: 12’d586: 12’d587: 12’d588: 12’d589: 12’d590: 12’d591: 12’
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614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 12’d602: 12’d603: 12’d604: 12’d605: 12’d606: 12’d607: 12’d608: 12’d609: 12’d610: 12’d611: 12’d612: 12’d613: 12’d614: 12’d615: 12’d616: 12’d617: 12’d618: 12’d619: 12’d620: 12’d621: 12’d622: 12’d623: 12’d624: 12’d625: 12’d626: 12’d627: 12’d628: 12’d629: 12’d630: 12’d631: 12’d632: 12’d633: 12’d634: 12’d635: 12’d636: 12’d637: 12’
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660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 12’d648: 12’d649: 12’d650: 12’d651: 12’d652: 12’d653: 12’d654: 12’d655: 12’d656: 12’d657: 12’d658: 12’d659: 12’d660: 12’d661: 12’d662: 12’d663: 12’d664: 12’d665: 12’d666: 12’d667: 12’d668: 12’d669: 12’d670: 12’d671: 12’d672: 12’d673: 12’d674: 12’d675: 12’d676: 12’d677: 12’d678: 12’d679: 12’d680: 12’d681: 12’d682: 12’d683: 12’
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706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 12’d694: 12’d695: 12’d696: 12’d697: 12’d698: 12’d699: 12’d700: 12’d701: 12’d702: 12’d703: 12’d704: 12’d705: 12’d706: 12’d707: 12’d708: 12’d709: 12’d710: 12’d711: 12’d712: 12’d713: 12’d714: 12’d715: 12’d716: 12’d717: 12’d718: 12’d719: 12’d720: 12’d721: 12’d722: 12’d723: 12’d724: 12’d725: 12’d726: 12’d727: 12’d728: 12’d729: 12’
PAGE 143
752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 12’d740: 12’d741: 12’d742: 12’d743: 12’d744: 12’d745: 12’d746: 12’d747: 12’d748: 12’d749: 12’d750: 12’d751: 12’d752: 12’d753: 12’d754: 12’d755: 12’d756: 12’d757: 12’d758: 12’d759: 12’d760: 12’d761: 12’d762: 12’d763: 12’d764: 12’d765: 12’d766: 12’d767: 12’d768: 12’d769: 12’d770: 12’d771: 12’d772: 12’d773: 12’d774: 12’d775: 12’
PAGE 144
798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 12’d786: 12’d787: 12’d788: 12’d789: 12’d790: 12’d791: 12’d792: 12’d793: 12’d794: 12’d795: 12’d796: 12’d797: 12’d798: 12’d799: 12’d800: 12’d801: 12’d802: 12’d803: 12’d804: 12’d805: 12’d806: 12’d807: 12’d808: 12’d809: 12’d810: 12’d811: 12’d812: 12’d813: 12’d814: 12’d815: 12’d816: 12’d817: 12’d818: 12’d819: 12’d820: 12’d821: 12’
PAGE 145
844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 12’d832: 12’d833: 12’d834: 12’d835: 12’d836: 12’d837: 12’d838: 12’d839: 12’d840: 12’d841: 12’d842: 12’d843: 12’d844: 12’d845: 12’d846: 12’d847: 12’d848: 12’d849: 12’d850: 12’d851: 12’d852: 12’d853: 12’d854: 12’d855: 12’d856: 12’d857: 12’d858: 12’d859: 12’d860: 12’d861: 12’d862: 12’d863: 12’d864: 12’d865: 12’d866: 12’d867: 12’
PAGE 146
890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 12’d878: 12’d879: 12’d880: 12’d881: 12’d882: 12’d883: 12’d884: 12’d885: 12’d886: 12’d887: 12’d888: 12’d889: 12’d890: 12’d891: 12’d892: 12’d893: 12’d894: 12’d895: 12’d896: 12’d897: 12’d898: 12’d899: 12’d900: 12’d901: 12’d902: 12’d903: 12’d904: 12’d905: 12’d906: 12’d907: 12’d908: 12’d909: 12’d910: 12’d911: 12’d912: 12’d913: 12’
PAGE 147
936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 12’d924: 12’d925: 12’d926: 12’d927: 12’d928: 12’d929: 12’d930: 12’d931: 12’d932: 12’d933: 12’d934: 12’d935: 12’d936: 12’d937: 12’d938: 12’d939: 12’d940: 12’d941: 12’d942: 12’d943: 12’d944: 12’d945: 12’d946: 12’d947: 12’d948: 12’d949: 12’d950: 12’d951: 12’d952: 12’d953: 12’d954: 12’d955: 12’d956: 12’d957: 12’d958: 12’d959: 12’
PAGE 148
982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 12’d970: quad_corners = 76’d166903815503556664320; 12’d971: quad_corners = 76’d166903815503556664320; 12’d972: quad_corners = 76’d166903815503556664320; 12’d973: quad_corners = 76’d166903815503556664320; 12’d974: quad_corners = 76’d166903815503556664320; 12’d975: quad_corners = 76’d1669038155035566
PAGE 149
1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 12’d1016: 12’d1017: 12’d1018: 12’d1019: 12’d1020: 12’d1021: 12’d1022: 12’d1023: 12’d1024: 12’d1025: 12’d1026: 12’d1027: 12’d1028: 12’d1029: 12’d1030: 12’d1031: 12’d1032: 12’d1033: 12’d1034: 12’d1035: 12’d1036: 12’d1037: 12’d1038: 12’d1039: 12’d1040: 12’d1041: 12’d1042: 12’d1043: 1
PAGE 150
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 12’d1062: 12’d1063: 12’d1064: 12’d1065: 12’d1066: 12’d1067: 12’d1068: 12’d1069: 12’d1070: 12’d1071: 12’d1072: 12’d1073: 12’d1074: 12’d1075: 12’d1076: 12’d1077: 12’d1078: 12’d1079: 12’d1080: 12’d1081: 12’d1082: 12’d1083: 12’d1084: 12’d1085: 12’d1086: 12’d1087: 12’d1088: 12’d1089: 1
PAGE 151
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 12’d1108: 12’d1109: 12’d1110: 12’d1111: 12’d1112: 12’d1113: 12’d1114: 12’d1115: 12’d1116: 12’d1117: 12’d1118: 12’d1119: 12’d1120: 12’d1121: 12’d1122: 12’d1123: 12’d1124: 12’d1125: 12’d1126: 12’d1127: 12’d1128: 12’d1129: 12’d1130: 12’d1131: 12’d1132: 12’d1133: 12’d1134: 12’d1135: 1
PAGE 152
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 12’d1154: 12’d1155: 12’d1156: 12’d1157: 12’d1158: 12’d1159: 12’d1160: 12’d1161: 12’d1162: 12’d1163: 12’d1164: 12’d1165: 12’d1166: 12’d1167: 12’d1168: 12’d1169: 12’d1170: 12’d1171: 12’d1172: 12’d1173: 12’d1174: 12’d1175: 12’d1176: 12’d1177: 12’d1178: 12’d1179: 12’d1180: 12’d1181: 1
PAGE 153
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 12’d1200: 12’d1201: 12’d1202: 12’d1203: 12’d1204: 12’d1205: 12’d1206: 12’d1207: 12’d1208: 12’d1209: 12’d1210: 12’d1211: 12’d1212: 12’d1213: 12’d1214: 12’d1215: 12’d1216: 12’d1217: 12’d1218: 12’d1219: 12’d1220: 12’d1221: 12’d1222: 12’d1223: 12’d1224: 12’d1225: 12’d1226: 12’d1227: 1
PAGE 154
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 12’d1246: 12’d1247: 12’d1248: 12’d1249: 12’d1250: 12’d1251: 12’d1252: 12’d1253: 12’d1254: 12’d1255: 12’d1256: 12’d1257: 12’d1258: 12’d1259: 12’d1260: 12’d1261: 12’d1262: 12’d1263: 12’d1264: 12’d1265: 12’d1266: 12’d1267: 12’d1268: 12’d1269: 12’d1270: 12’d1271: 12’d1272: 12’d1273: 1
PAGE 155
1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 12’d1292: 12’d1293: 12’d1294: 12’d1295: 12’d1296: 12’d1297: 12’d1298: 12’d1299: 12’d1300: 12’d1301: 12’d1302: 12’d1303: 12’d1304: 12’d1305: 12’d1306: 12’d1307: 12’d1308: 12’d1309: 12’d1310: 12’d1311: 12’d1312: 12’d1313: 12’d1314: 12’d1315: 12’d1316: 12’d1317: 12’d1318: 12’d1319: 1
PAGE 156
1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 12’d1338: 12’d1339: 12’d1340: 12’d1341: 12’d1342: 12’d1343: 12’d1344: 12’d1345: 12’d1346: 12’d1347: 12’d1348: 12’d1349: 12’d1350: 12’d1351: 12’d1352: 12’d1353: 12’d1354: 12’d1355: 12’d1356: 12’d1357: 12’d1358: 12’d1359: 12’d1360: 12’d1361: 12’d1362: 12’d1363: 12’d1364: 12’d1365: 1
PAGE 157
1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 12’d1384: 12’d1385: 12’d1386: 12’d1387: 12’d1388: 12’d1389: 12’d1390: 12’d1391: 12’d1392: 12’d1393: 12’d1394: 12’d1395: 12’d1396: 12’d1397: 12’d1398: 12’d1399: 12’d1400: 12’d1401: 12’d1402: 12’d1403: 12’d1404: 12’d1405: 12’d1406: 12’d1407: 12’d1408: 12’d1409: 12’d1410: 12’d1411: 1
PAGE 158
1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 12’d1430: 12’d1431: 12’d1432: 12’d1433: 12’d1434: 12’d1435: 12’d1436: 12’d1437: 12’d1438: 12’d1439: 12’d1440: 12’d1441: 12’d1442: 12’d1443: 12’d1444: 12’d1445: 12’d1446: 12’d1447: 12’d1448: 12’d1449: 12’d1450: 12’d1451: 12’d1452: 12’d1453: 12’d1454: 12’d1455: 12’d1456: 12’d1457: 1
PAGE 159
1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 12’d1476: 12’d1477: 12’d1478: 12’d1479: 12’d1480: 12’d1481: 12’d1482: 12’d1483: 12’d1484: 12’d1485: 12’d1486: 12’d1487: 12’d1488: 12’d1489: 12’d1490: 12’d1491: 12’d1492: 12’d1493: 12’d1494: 12’d1495: 12’d1496: 12’d1497: 12’d1498: 12’d1499: 12’d1500: 12’d1501: 12’d1502: 12’d1503: 1
PAGE 160
1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 12’d1522: 12’d1523: 12’d1524: 12’d1525: 12’d1526: 12’d1527: 12’d1528: 12’d1529: 12’d1530: 12’d1531: 12’d1532: 12’d1533: 12’d1534: 12’d1535: 12’d1536: 12’d1537: 12’d1538: 12’d1539: 12’d1540: 12’d1541: 12’d1542: 12’d1543: 12’d1544: 12’d1545: 12’d1546: 12’d1547: 12’d1548: 12’d1549: 1
PAGE 161
1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 12’d1568: 12’d1569: 12’d1570: 12’d1571: 12’d1572: 12’d1573: 12’d1574: 12’d1575: 12’d1576: 12’d1577: 12’d1578: 12’d1579: 12’d1580: 12’d1581: 12’d1582: 12’d1583: 12’d1584: 12’d1585: 12’d1586: 12’d1587: 12’d1588: 12’d1589: 12’d1590: 12’d1591: 12’d1592: 12’d1593: 12’d1594: 12’d1595: 1
PAGE 162
6 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 12’d1614: 12’d1615: 12’d1616: 12’d1617: 12’d1618: 12’d1619: 12’d1620: 12’d1621: 12’d1622: 12’d1623: 12’d1624: 12’d1625: 12’d1626: 12’d1627: 12’d1628: 12’d1629: 12’d1630: 12’d1631: 12’d1632: 12’d1633: 12’d1634: 12’d1635: 12’d1636: 12’d1637: 12’d1638: 12’d1639: 12’d1640: 12’d1641: 1
PAGE 163
1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 12’d1660: 12’d1661: 12’d1662: 12’d1663: 12’d1664: 12’d1665: 12’d1666: 12’d1667: 12’d1668: 12’d1669: 12’d1670: 12’d1671: 12’d1672: 12’d1673: 12’d1674: 12’d1675: 12’d1676: 12’d1677: 12’d1678: 12’d1679: 12’d1680: 12’d1681: 12’d1682: 12’d1683: 12’d1684: 12’d1685: 12’d1686: 12’d1687: 1
PAGE 164
1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 12’d1706: 12’d1707: 12’d1708: 12’d1709: 12’d1710: 12’d1711: 12’d1712: 12’d1713: 12’d1714: 12’d1715: 12’d1716: 12’d1717: 12’d1718: 12’d1719: 12’d1720: 12’d1721: 12’d1722: 12’d1723: 12’d1724: 12’d1725: 12’d1726: 12’d1727: 12’d1728: 12’d1729: 12’d1730: 12’d1731: 12’d1732: 12’d1733: 1
PAGE 165
1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 12’d1752: 12’d1753: 12’d1754: 12’d1755: 12’d1756: 12’d1757: 12’d1758: 12’d1759: 12’d1760: 12’d1761: 12’d1762: 12’d1763: 12’d1764: 12’d1765: 12’d1766: 12’d1767: 12’d1768: 12’d1769: 12’d1770: 12’d1771: 12’d1772: 12’d1773: 12’d1774: 12’d1775: 12’d1776: 12’d1777: 12’d1778: 12’d1779: 1
PAGE 166
1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 12’d1798: 12’d1799: 12’d1800: 12’d1801: 12’d1802: 12’d1803: 12’d1804: 12’d1805: 12’d1806: 12’d1807: 12’d1808: 12’d1809: 12’d1810: 12’d1811: 12’d1812: 12’d1813: 12’d1814: 12’d1815: 12’d1816: 12’d1817: 12’d1818: 12’d1819: 12’d1820: 12’d1821: 12’d1822: 12’d1823: 12’d1824: 12’d1825: 1
PAGE 167
1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 12’d1844: 12’d1845: 12’d1846: 12’d1847: 12’d1848: 12’d1849: 12’d1850: 12’d1851: 12’d1852: 12’d1853: 12’d1854: 12’d1855: 12’d1856: 12’d1857: 12’d1858: 12’d1859: 12’d1860: 12’d1861: 12’d1862: 12’d1863: 12’d1864: 12’d1865: 12’d1866: 12’d1867: 12’d1868: 12’d1869: 12’d1870: 12’d1871: 1
PAGE 168
1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 12’d1890: 12’d1891: 12’d1892: 12’d1893: 12’d1894: 12’d1895: 12’d1896: 12’d1897: 12’d1898: 12’d1899: 12’d1900: 12’d1901: 12’d1902: 12’d1903: 12’d1904: 12’d1905: 12’d1906: 12’d1907: 12’d1908: 12’d1909: 12’d1910: 12’d1911: 12’d1912: 12’d1913: 12’d1914: 12’d1915: 12’d1916: 12’d1917: 1
PAGE 169
1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 12’d1936: 12’d1937: 12’d1938: 12’d1939: 12’d1940: 12’d1941: 12’d1942: 12’d1943: 12’d1944: 12’d1945: 12’d1946: 12’d1947: 12’d1948: 12’d1949: 12’d1950: 12’d1951: 12’d1952: 12’d1953: 12’d1954: 12’d1955: 12’d1956: 12’d1957: 12’d1958: 12’d1959: 12’d1960: 12’d1961: 12’d1962: 12’d1963: 1
PAGE 170
1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 12’d1982: 12’d1983: 12’d1984: 12’d1985: 12’d1986: 12’d1987: 12’d1988: 12’d1989: 12’d1990: 12’d1991: 12’d1992: 12’d1993: 12’d1994: 12’d1995: 12’d1996: 12’d1997: 12’d1998: 12’d1999: 12’d2000: 12’d2001: 12’d2002: 12’d2003: 12’d2004: 12’d2005: 12’d2006: 12’d2007: 12’d2008: 12’d2009: 1
PAGE 171
2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 12’d2028: 12’d2029: 12’d2030: 12’d2031: 12’d2032: 12’d2033: 12’d2034: 12’d2035: 12’d2036: 12’d2037: 12’d2038: 12’d2039: 12’d2040: 12’d2041: 12’d2042: 12’d2043: 12’d2044: 12’d2045: 12’d2046: 12’d2047: 12’d2048: 12’d2049: 12’d2050: 12’d2051: 12’d2052: 12’d2053: 12’d2054: 12’d2055: 1
PAGE 172
2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 12’d2074: 12’d2075: 12’d2076: 12’d2077: 12’d2078: 12’d2079: 12’d2080: 12’d2081: 12’d2082: 12’d2083: 12’d2084: 12’d2085: 12’d2086: 12’d2087: 12’d2088: 12’d2089: 12’d2090: 12’d2091: 12’d2092: 12’d2093: 12’d2094: 12’d2095: 12’d2096: 12’d2097: 12’d2098: 12’d2099: 12’d2100: 12’d2101: 1
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2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 12’d2120: 12’d2121: 12’d2122: 12’d2123: 12’d2124: 12’d2125: 12’d2126: 12’d2127: 12’d2128: 12’d2129: 12’d2130: 12’d2131: 12’d2132: 12’d2133: 12’d2134: 12’d2135: 12’d2136: 12’d2137: 12’d2138: 12’d2139: 12’d2140: 12’d2141: 12’d2142: 12’d2143: 12’d2144: 12’d2145: 12’d2146: 12’d2147: 1
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2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 12’d2166: 12’d2167: 12’d2168: 12’d2169: 12’d2170: 12’d2171: 12’d2172: 12’d2173: 12’d2174: 12’d2175: 12’d2176: 12’d2177: 12’d2178: 12’d2179: 12’d2180: 12’d2181: 12’d2182: 12’d2183: 12’d2184: 12’d2185: 12’d2186: 12’d2187: 12’d2188: 12’d2189: 12’d2190: 12’d2191: 12’d2192: 12’d2193: 1
PAGE 175
2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 12’d2212: 12’d2213: 12’d2214: 12’d2215: 12’d2216: 12’d2217: 12’d2218: 12’d2219: 12’d2220: 12’d2221: 12’d2222: 12’d2223: 12’d2224: 12’d2225: 12’d2226: 12’d2227: 12’d2228: 12’d2229: 12’d2230: 12’d2231: 12’d2232: 12’d2233: 12’d2234: 12’d2235: 12’d2236: 12’d2237: 12’d2238: 12’d2239: 1
PAGE 176
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 12’d2258: 12’d2259: 12’d2260: 12’d2261: 12’d2262: 12’d2263: 12’d2264: 12’d2265: 12’d2266: 12’d2267: 12’d2268: 12’d2269: 12’d2270: 12’d2271: 12’d2272: 12’d2273: 12’d2274: 12’d2275: 12’d2276: 12’d2277: 12’d2278: 12’d2279: 12’d2280: 12’d2281: 12’d2282: 12’d2283: 12’d2284: 12’d2285: 1
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2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 12’d2304: 12’d2305: 12’d2306: 12’d2307: 12’d2308: 12’d2309: 12’d2310: 12’d2311: 12’d2312: 12’d2313: 12’d2314: 12’d2315: 12’d2316: 12’d2317: 12’d2318: 12’d2319: 12’d2320: 12’d2321: 12’d2322: 12’d2323: 12’d2324: 12’d2325: 12’d2326: 12’d2327: 12’d2328: 12’d2329: 12’d2330: 12’d2331: 1
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2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 12’d2350: 12’d2351: 12’d2352: 12’d2353: 12’d2354: 12’d2355: 12’d2356: 12’d2357: 12’d2358: 12’d2359: 12’d2360: 12’d2361: 12’d2362: 12’d2363: 12’d2364: 12’d2365: 12’d2366: 12’d2367: 12’d2368: 12’d2369: 12’d2370: 12’d2371: 12’d2372: 12’d2373: 12’d2374: 12’d2375: 12’d2376: 12’d2377: 1
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2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 12’d2396: 12’d2397: 12’d2398: 12’d2399: 12’d2400: 12’d2401: 12’d2402: 12’d2403: 12’d2404: 12’d2405: 12’d2406: 12’d2407: 12’d2408: 12’d2409: 12’d2410: 12’d2411: 12’d2412: 12’d2413: 12’d2414: 12’d2415: 12’d2416: 12’d2417: 12’d2418: 12’d2419: 12’d2420: 12’d2421: 12’d2422: 12’d2423: 1
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2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 12’d2442: 12’d2443: 12’d2444: 12’d2445: 12’d2446: 12’d2447: 12’d2448: 12’d2449: 12’d2450: 12’d2451: 12’d2452: 12’d2453: 12’d2454: 12’d2455: 12’d2456: 12’d2457: 12’d2458: 12’d2459: 12’d2460: 12’d2461: 12’d2462: 12’d2463: 12’d2464: 12’d2465: 12’d2466: 12’d2467: 12’d2468: 12’d2469: 1
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2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 12’d2488: 12’d2489: 12’d2490: 12’d2491: 12’d2492: 12’d2493: 12’d2494: 12’d2495: 12’d2496: 12’d2497: 12’d2498: 12’d2499: 12’d2500: 12’d2501: 12’d2502: 12’d2503: 12’d2504: 12’d2505: 12’d2506: 12’d2507: 12’d2508: 12’d2509: 12’d2510: 12’d2511: 12’d2512: 12’d2513: 12’d2514: 12’d2515: 1
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2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 12’d2534: 12’d2535: 12’d2536: 12’d2537: 12’d2538: 12’d2539: 12’d2540: 12’d2541: 12’d2542: 12’d2543: 12’d2544: 12’d2545: 12’d2546: 12’d2547: 12’d2548: 12’d2549: 12’d2550: 12’d2551: 12’d2552: 12’d2553: 12’d2554: 12’d2555: 12’d2556: 12’d2557: 12’d2558: 12’d2559: 12’d2560: 12’d2561: 1
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2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 12’d2580: 12’d2581: 12’d2582: 12’d2583: 12’d2584: 12’d2585: 12’d2586: 12’d2587: 12’d2588: 12’d2589: 12’d2590: 12’d2591: 12’d2592: 12’d2593: 12’d2594: 12’d2595: 12’d2596: 12’d2597: 12’d2598: 12’d2599: 12’d2600: 12’d2601: 12’d2602: 12’d2603: 12’d2604: 12’d2605: 12’d2606: 12’d2607: 1
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2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 12’d2626: 12’d2627: 12’d2628: 12’d2629: 12’d2630: 12’d2631: 12’d2632: 12’d2633: 12’d2634: 12’d2635: 12’d2636: 12’d2637: 12’d2638: 12’d2639: 12’d2640: 12’d2641: 12’d2642: 12’d2643: 12’d2644: 12’d2645: 12’d2646: 12’d2647: 12’d2648: 12’d2649: 12’d2650: 12’d2651: 12’d2652: 12’d2653: 1
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2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 12’d2672: 12’d2673: 12’d2674: 12’d2675: 12’d2676: 12’d2677: 12’d2678: 12’d2679: 12’d2680: 12’d2681: 12’d2682: 12’d2683: 12’d2684: 12’d2685: 12’d2686: 12’d2687: 12’d2688: 12’d2689: 12’d2690: 12’d2691: 12’d2692: 12’d2693: 12’d2694: 12’d2695: 12’d2696: 12’d2697: 12’d2698: 12’d2699: 1
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2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 12’d2718: 12’d2719: 12’d2720: 12’d2721: 12’d2722: 12’d2723: 12’d2724: 12’d2725: 12’d2726: 12’d2727: 12’d2728: 12’d2729: 12’d2730: 12’d2731: 12’d2732: 12’d2733: 12’d2734: 12’d2735: 12’d2736: 12’d2737: 12’d2738: 12’d2739: 12’d2740: 12’d2741: 12’d2742: 12’d2743: 12’d2744: 12’d2745: 1
PAGE 187
2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 12’d2764: 12’d2765: 12’d2766: 12’d2767: 12’d2768: 12’d2769: 12’d2770: 12’d2771: 12’d2772: 12’d2773: 12’d2774: 12’d2775: 12’d2776: 12’d2777: 12’d2778: 12’d2779: 12’d2780: 12’d2781: 12’d2782: 12’d2783: 12’d2784: 12’d2785: 12’d2786: 12’d2787: 12’d2788: 12’d2789: 12’d2790: 12’d2791: 1
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2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 12’d2810: 12’d2811: 12’d2812: 12’d2813: 12’d2814: 12’d2815: 12’d2816: 12’d2817: 12’d2818: 12’d2819: 12’d2820: 12’d2821: 12’d2822: 12’d2823: 12’d2824: 12’d2825: 12’d2826: 12’d2827: 12’d2828: 12’d2829: 12’d2830: 12’d2831: 12’d2832: 12’d2833: 12’d2834: 12’d2835: 12’d2836: 12’d2837: 1
PAGE 189
2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 12’d2856: 12’d2857: 12’d2858: 12’d2859: 12’d2860: 12’d2861: 12’d2862: 12’d2863: 12’d2864: 12’d2865: 12’d2866: 12’d2867: 12’d2868: 12’d2869: 12’d2870: 12’d2871: 12’d2872: 12’d2873: 12’d2874: 12’d2875: 12’d2876: 12’d2877: 12’d2878: 12’d2879: 12’d2880: 12’d2881: 12’d2882: 12’d2883: 1
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2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 12’d2902: 12’d2903: 12’d2904: 12’d2905: 12’d2906: 12’d2907: 12’d2908: 12’d2909: 12’d2910: 12’d2911: 12’d2912: 12’d2913: 12’d2914: 12’d2915: 12’d2916: 12’d2917: 12’d2918: 12’d2919: 12’d2920: 12’d2921: 12’d2922: 12’d2923: 12’d2924: 12’d2925: 12’d2926: 12’d2927: 12’d2928: 12’d2929: 1
PAGE 191
2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 12’d2948: 12’d2949: 12’d2950: 12’d2951: 12’d2952: 12’d2953: 12’d2954: 12’d2955: 12’d2956: 12’d2957: 12’d2958: 12’d2959: 12’d2960: 12’d2961: 12’d2962: 12’d2963: 12’d2964: 12’d2965: 12’d2966: 12’d2967: 12’d2968: 12’d2969: 12’d2970: 12’d2971: 12’d2972: 12’d2973: 12’d2974: 12’d2975: 1
PAGE 192
3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 12’d2994: 12’d2995: 12’d2996: 12’d2997: 12’d2998: 12’d2999: 12’d3000: 12’d3001: 12’d3002: 12’d3003: 12’d3004: 12’d3005: 12’d3006: 12’d3007: 12’d3008: 12’d3009: 12’d3010: 12’d3011: 12’d3012: 12’d3013: 12’d3014: 12’d3015: 12’d3016: 12’d3017: 12’d3018: 12’d3019: 12’d3020: 12’d3021: 1
PAGE 193
3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 12’d3040: 12’d3041: 12’d3042: 12’d3043: 12’d3044: 12’d3045: 12’d3046: 12’d3047: 12’d3048: 12’d3049: 12’d3050: 12’d3051: 12’d3052: 12’d3053: 12’d3054: 12’d3055: 12’d3056: 12’d3057: 12’d3058: 12’d3059: 12’d3060: 12’d3061: 12’d3062: 12’d3063: 12’d3064: 12’d3065: 12’d3066: 12’d3067: 1
PAGE 194
3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 12’d3086: 12’d3087: 12’d3088: 12’d3089: 12’d3090: 12’d3091: 12’d3092: 12’d3093: 12’d3094: 12’d3095: 12’d3096: 12’d3097: 12’d3098: 12’d3099: 12’d3100: 12’d3101: 12’d3102: 12’d3103: 12’d3104: 12’d3105: 12’d3106: 12’d3107: 12’d3108: 12’d3109: 12’d3110: 12’d3111: 12’d3112: 12’d3113: 1
PAGE 195
3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 12’d3132: 12’d3133: 12’d3134: 12’d3135: 12’d3136: 12’d3137: 12’d3138: 12’d3139: 12’d3140: 12’d3141: 12’d3142: 12’d3143: 12’d3144: 12’d3145: 12’d3146: 12’d3147: 12’d3148: 12’d3149: 12’d3150: 12’d3151: 12’d3152: 12’d3153: 12’d3154: 12’d3155: 12’d3156: 12’d3157: 12’d3158: 12’d3159: 1
PAGE 196
3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 12’d3178: 12’d3179: 12’d3180: 12’d3181: 12’d3182: 12’d3183: 12’d3184: 12’d3185: 12’d3186: 12’d3187: 12’d3188: 12’d3189: 12’d3190: 12’d3191: 12’d3192: 12’d3193: 12’d3194: 12’d3195: 12’d3196: 12’d3197: 12’d3198: 12’d3199: 12’d3200: 12’d3201: 12’d3202: 12’d3203: 12’d3204: 12’d3205: 1
PAGE 197
3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 12’d3224: 12’d3225: 12’d3226: 12’d3227: 12’d3228: 12’d3229: 12’d3230: 12’d3231: 12’d3232: 12’d3233: 12’d3234: 12’d3235: 12’d3236: 12’d3237: 12’d3238: 12’d3239: 12’d3240: 12’d3241: 12’d3242: 12’d3243: 12’d3244: 12’d3245: 12’d3246: 12’d3247: 12’d3248: 12’d3249: 12’d3250: 12’d3251: 1
PAGE 198
3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 12’d3270: 12’d3271: 12’d3272: 12’d3273: 12’d3274: 12’d3275: 12’d3276: 12’d3277: 12’d3278: 12’d3279: 12’d3280: 12’d3281: 12’d3282: 12’d3283: 12’d3284: 12’d3285: 12’d3286: 12’d3287: 12’d3288: 12’d3289: 12’d3290: 12’d3291: 12’d3292: 12’d3293: 12’d3294: 12’d3295: 12’d3296: 12’d3297: 1
PAGE 199
3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 12’d3316: 12’d3317: 12’d3318: 12’d3319: 12’d3320: 12’d3321: 12’d3322: 12’d3323: 12’d3324: 12’d3325: 12’d3326: 12’d3327: 12’d3328: 12’d3329: 12’d3330: 12’d3331: 12’d3332: 12’d3333: 12’d3334: 12’d3335: 12’d3336: 12’d3337: 12’d3338: 12’d3339: 12’d3340: 12’d3341: 12’d3342: 12’d3343: 1
PAGE 200
3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 12’d3362: 12’d3363: 12’d3364: 12’d3365: 12’d3366: 12’d3367: 12’d3368: 12’d3369: 12’d3370: 12’d3371: 12’d3372: 12’d3373: 12’d3374: 12’d3375: 12’d3376: 12’d3377: 12’d3378: 12’d3379: 12’d3380: 12’d3381: 12’d3382: 12’d3383: 12’d3384: 12’d3385: 12’d3386: 12’d3387: 12’d3388: 12’d3389: 1
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3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 12’d3408: 12’d3409: 12’d3410: 12’d3411: 12’d3412: 12’d3413: 12’d3414: 12’d3415: 12’d3416: 12’d3417: 12’d3418: 12’d3419: 12’d3420: 12’d3421: 12’d3422: 12’d3423: 12’d3424: 12’d3425: 12’d3426: 12’d3427: 12’d3428: 12’d3429: 12’d3430: 12’d3431: 12’d3432: 12’d3433: 12’d3434: 12’d3435: 1
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3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 12’d3454: 12’d3455: 12’d3456: 12’d3457: 12’d3458: 12’d3459: 12’d3460: 12’d3461: 12’d3462: 12’d3463: 12’d3464: 12’d3465: 12’d3466: 12’d3467: 12’d3468: 12’d3469: 12’d3470: 12’d3471: 12’d3472: 12’d3473: 12’d3474: 12’d3475: 12’d3476: 12’d3477: 12’d3478: 12’d3479: 12’d3480: 12’d3481: 1
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3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 12’d3500: 12’d3501: 12’d3502: 12’d3503: 12’d3504: 12’d3505: 12’d3506: 12’d3507: 12’d3508: 12’d3509: 12’d3510: 12’d3511: 12’d3512: 12’d3513: 12’d3514: 12’d3515: 12’d3516: 12’d3517: 12’d3518: 12’d3519: 12’d3520: 12’d3521: 12’d3522: 12’d3523: 12’d3524: 12’d3525: 12’d3526: 12’d3527: 1
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3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 12’d3546: 12’d3547: 12’d3548: 12’d3549: 12’d3550: 12’d3551: 12’d3552: 12’d3553: 12’d3554: 12’d3555: 12’d3556: 12’d3557: 12’d3558: 12’d3559: 12’d3560: 12’d3561: 12’d3562: 12’d3563: 12’d3564: 12’d3565: 12’d3566: 12’d3567: 12’d3568: 12’d3569: 12’d3570: 12’d3571: 12’d3572: 12’d3573: 1
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3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 12’d3592: 12’d3593: 12’d3594: 12’d3595: 12’d3596: 12’d3597: 12’d3598: 12’d3599: 12’d3600: 12’d3601: 12’d3602: 12’d3603: 12’d3604: 12’d3605: 12’d3606: 12’d3607: 12’d3608: 12’d3609: 12’d3610: 12’d3611: 12’d3612: 12’d3613: 12’d3614: 12’d3615: 12’d3616: 12’d3617: 12’d3618: 12’d3619: 1
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3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 12’d3638: 12’d3639: 12’d3640: 12’d3641: 12’d3642: 12’d3643: 12’d3644: 12’d3645: 12’d3646: 12’d3647: 12’d3648: 12’d3649: 12’d3650: 12’d3651: 12’d3652: 12’d3653: 12’d3654: 12’d3655: 12’d3656: 12’d3657: 12’d3658: 12’d3659: 12’d3660: 12’d3661: 12’d3662: 12’d3663: 12’d3664: 12’d3665: 1
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3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 12’d3684: 12’d3685: 12’d3686: 12’d3687: 12’d3688: 12’d3689: 12’d3690: 12’d3691: 12’d3692: 12’d3693: 12’d3694: 12’d3695: 12’d3696: 12’d3697: 12’d3698: 12’d3699: 12’d3700: 12’d3701: 12’d3702: 12’d3703: 12’d3704: 12’d3705: 12’d3706: 12’d3707: 12’d3708: 12’d3709: 12’d3710: 12’d3711: 1
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3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 12’d3730: 12’d3731: 12’d3732: 12’d3733: 12’d3734: 12’d3735: 12’d3736: 12’d3737: 12’d3738: 12’d3739: 12’d3740: 12’d3741: 12’d3742: 12’d3743: 12’d3744: 12’d3745: 12’d3746: 12’d3747: 12’d3748: 12’d3749: 12’d3750: 12’d3751: 12’d3752: 12’d3753: 12’d3754: 12’d3755: 12’d3756: 12’d3757: 1
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3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 12’d3776: 12’d3777: 12’d3778: 12’d3779: 12’d3780: 12’d3781: 12’d3782: 12’d3783: 12’d3784: 12’d3785: 12’d3786: 12’d3787: 12’d3788: 12’d3789: 12’d3790: 12’d3791: 12’d3792: 12’d3793: 12’d3794: 12’d3795: 12’d3796: 12’d3797: 12’d3798: 12’d3799: 12’d3800: 12’d3801: 12’d3802: 12’d3803: 1
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3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 12’d3822: 12’d3823: 12’d3824: 12’d3825: 12’d3826: 12’d3827: 12’d3828: 12’d3829: 12’d3830: 12’d3831: 12’d3832: 12’d3833: 12’d3834: 12’d3835: 12’d3836: 12’d3837: 12’d3838: 12’d3839: 12’d3840: 12’d3841: 12’d3842: 12’d3843: 12’d3844: 12’d3845: 12’d3846: 12’d3847: 12’d3848: 12’d3849: 1
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3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 12’d3868: 12’d3869: 12’d3870: 12’d3871: 12’d3872: 12’d3873: 12’d3874: 12’d3875: 12’d3876: 12’d3877: 12’d3878: 12’d3879: 12’d3880: 12’d3881: 12’d3882: 12’d3883: 12’d3884: 12’d3885: 12’d3886: 12’d3887: 12’d3888: 12’d3889: 12’d3890: 12’d3891: 12’d3892: 12’d3893: 12’d3894: 12’d3895: 1
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3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 12’d3914: 12’d3915: 12’d3916: 12’d3917: 12’d3918: 12’d3919: 12’d3920: 12’d3921: 12’d3922: 12’d3923: 12’d3924: 12’d3925: 12’d3926: 12’d3927: 12’d3928: 12’d3929: 12’d3930: 12’d3931: 12’d3932: 12’d3933: 12’d3934: 12’d3935: 12’d3936: 12’d3937: 12’d3938: 12’d3939: 12’d3940: 12’d3941: 1
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3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 12’d3960: 12’d3961: 12’d3962: 12’d3963: 12’d3964: 12’d3965: 12’d3966: 12’d3967: 12’d3968: 12’d3969: 12’d3970: 12’d3971: 12’d3972: 12’d3973: 12’d3974: 12’d3975: 12’d3976: 12’d3977: 12’d3978: 12’d3979: 12’d3980: 12’d3981: 12’d3982: 12’d3983: 12’d3984: 12’d3985: 12’d3986: 12’d3987: 1
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4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 12’d4006: 12’d4007: 12’d4008: 12’d4009: 12’d4010: 12’d4011: 12’d4012: 12’d4013: 12’d4014: 12’d4015: 12’d4016: 12’d4017: 12’d4018: 12’d4019: 12’d4020: 12’d4021: 12’d4022: 12’d4023: 12’d4024: 12’d4025: 12’d4026: 12’d4027: 12’d4028: 12’d4029: 12’d4030: 12’d4031: 12’d4032: 12’d4033: 1
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12’d4052: 12’d4053: 12’d4054: 12’d4055: 12’d4056: 12’d4057: 12’d4058: 12’d4059: 12’d4060: 12’d4061: 12’d4062: 12’d4063: 12’d4064: 12’d4065: 12’d4066: 12’d4067: 12’d4068: 12’d4069: 12’d4070: 12’d4071: 12’d4072: 12’d4073: 12’d4074: 12’d4075: 12’d4076: 12’d4077: 12’d4078: 12’d4079: 12’d4080: 12’d4081: 12’d4082: 12’d4083: 12’d4084: 12’d4085: 12’d4086: 12’d4087: 12’d4088: 12’d4089: 12’d4090: 12’d4091: 12’d4092: 12’d4093: 12’d4094: 12’d4095: 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4
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4110 endmodule A.3.3 1 2 3 4 5 6 7 8 accel lut.jl #= This script generates an accel_lut.v file. accel_lut.v contains a verilog implementation of a lookup table, which takes in an accelerometer reading (6 bit x dir, 6 bit y dir), and looks up a 76 bit value (4 corners of quadrilateral) This script requires a input file accel_lut.txt containing data points. It then interpolates the data points using 2D splines, and creates the desired lookup table. 9 10 11 Format of accel_lut.
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43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 function parse_data(path) raw_data = read_file(path) num_samples = size(raw_data)[1] x_accel = zeros(Int64, num_samples) y_accel = zeros(Int64, num_samples) x1 = zeros(Int64, num_samples) y1 = zeros(Int64, num_samples) x2 = zeros(Int64, num_samples) y2 = zeros(Int64, num_samples) x3 = zeros(Int64, num_samples) y3 = zeros(Int64, num_samples) x4 = zeros(Int64, num_samples) y4 = zeros(Int64, num_samples) base = 16 for i = 1:nu
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x[i+1] = i >> 6 y[i+1] = i & ((1 << 6) - 1) 89 90 91 end 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 # do the spline interpolation # we do linear fits for now # as we add more points, we can do something more sophisticated x_deg = 2; y_deg = 2; # we also use a smoothing factor # this trades off exact interpolation vs weighted least squares # for more details, see doc at: https://github.com/kbarbary/Dierckx.jl smooth_factor = 454.
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for i=1:2^12 quad_corners[i] = y4_interp[i] + (x4_interp[i] << 9) + (y3_interp[i] << 19) + (x3_in quad_corners[i] += (y2_interp[i] << 38) + (x2_interp[i] << 47) + (y1_interp[i] << 57 end 135 136 137 138 139 # write header comment_head = "//////////////////////////////////////////////////////////////////////// comment_body1 = "//This file was autogenerated by accel_lut.jl.
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10 11 12 18,20, 10,20, 20,18, A.3.5 1 2 3 4 5 6 7 8 0,33, 0,07e, 8,0, 3b,1df, 60,1df, 16,1df, 27f,1a5, 27f,158, 26a,1df, 249,0 21b,0 27f,0 pixels kept.v //////////////////////////////////////////////////////////////////////////////////////////// // pixels_kept: Calculates the percentage of pixels lost, given the // coordinates of the four points of the quadrilateral.
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41 assign sy4 = {1’b0, y4}; 42 43 44 45 46 47 // difference terms assign d_x1_x3 = sx1 assign d_x2_x4 = sx2 assign d_y1_y3 = sy1 assign d_y2_y4 = sy2 - sx3; sx4; sy3; sy4; 48 49 50 51 // multipliers assign prod0 = d_x1_x3 * d_y2_y4; assign prod1 = d_y1_y3 * d_x2_x4; 52 53 54 // final area calculation assign prod = prod0 - prod1; // this is twice the area 55 56 57 58 // but first, we need to take its absolute value assign abs_prod = (prod < 0) ? -prod : prod; assign unsigned_prod = abs_prod; 59 6
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9 10 11 12 13 14 15 16 17 18 19 // unnecessary Coregen usage // // credits: http://danstrother.
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16 17 assign addr = (vcount[9:1] << 8) + (vcount[9:1] << 6) + (hcount >> 1); endmodule A.3.8 1 2 3 4 5 6 7 8 9 10 slow clk.v //////////////////////////////////////////////////////////////////////////////////////////// // this module generates a VERY SLOW clk by a simple counter // note: this method is NOT robust to timing issues, and for slowing // down/speeding up a clk by a reasonable multiple (e.
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13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 input up, input down, input left, input right, input override, input[1:0] switch, input[9:0] x1_raw, input[8:0] y1_raw, input[9:0] x2_raw, input[8:0] y2_raw, input[9:0] x3_raw, input[8:0] y3_raw, input[9:0] x4_raw, input[8:0] y4_raw, output reg[9:0] x1, output reg[8:0] y1, output reg[9:0] x2, output reg[8:0] y2, output reg[9:0] x3, output reg[8:0] y3, output reg[9:0] x4, output reg[8:0] y4, output reg[9:0] display_x, output reg[8:0] di
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2’b10: begin display_x display_y end 2’b11: begin display_x display_y end endcase 59 60 61 62 63 64 65 66 67 68 <= x3; <= y3; <= x4; <= y4; end 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 always @(posedge clk) begin if (override && !(cur_state == OVERRIDE)) begin cur_state <= OVERRIDE; x1 <= x1_raw; y1 <= y1_raw; x2 <= x2_raw; y2 <= y2_raw; x3 <= x3_raw; y3 <= y3_raw; x4 <= x4_raw; y4 <= y4_raw; end else if (override) begin case (swi
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105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 else if (left) begin x2 <= (x2 >= XSPEED) ? (x2 - XSPEED) : x2; end else if (right) begin x2 <= (x2 <= SCR_WIDTH-XSPEED) ? (x2 + XSPEED) : x2; end end 2’b10: begin if (down) begin y3 <= (y3 <= SCR_HEIGHT-YSPEED) ? (y3 + YSPEED) : y3; end else if (up) begin y3 <= (y3 >= YSPEED) ? (y3 - YSPEED) : y3; end else if (left) begin x3
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cur_state <= ~OVERRIDE; 151 end 152 153 end 154 155 endmodule A.3.10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 perspective params.
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39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 // // Future improvements: // 1) // This module uses over 120 out of 144 available 18x18 // multipliers!!! // By reducing bitwidths and avoiding needless multiplies, e.
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85 86 87 88 89 90 91 92 93 wire signed[9:0] sy1, sy2, sy3, sy4; assign sx1 = {1’b0, x1}; assign sx2 = {1’b0, x2}; assign sx3 = {1’b0, x3}; assign sx4 = {1’b0, x4}; assign sy1 = {1’b0, y1}; assign sy2 = {1’b0, y2}; assign sy3 = {1’b0, y3}; assign sy4 = {1’b0, y4}; 94 95 96 97 98 99 100 101 102 103 104 105 106 // difference values for computation wire signed[10:0] d_x1_x2,d_x2_x3,d_x3_x4,d_x4_x1; wire signed[9:0] d_y1_y2, d_y2_y3, d_y3_y4, d_y4_y1, d_y4_y2; assign d_x1_x2 = sx1 - sx2; assign d_x2_x3 = sx2
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131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 wire signed[25:0] denom_15; wire signed[32:0] p9; wire signed[32:0] x1_denom; wire signed[36:0] x1_denom_15; wire signed[43:0] p3; wire signed[31:0] y1_denom; wire signed[35:0] y1_denom_15; wire signed[42:0] p6; assign denom_15 = (denom <<< 4) - denom; // denom * 15 assign p9 = denom_15 <<< 7; // denom * 1920 assign x1_denom = sx1 * denom; // x1 * denom assign x1_denom_15 = (x1_denom <<< 4) - x1_denom; // x1 * denom * 15 assign p3 = x1_denom_1
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177 178 assign p4 = y4_p7 + d_y4_y1_denom_scale; assign p5 = y2_p8 - d_y1_y2_denom_scale; 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 // 36, 36, 44, 35, 35, 43, 24, 24, 33 // computation of inverse mapping wire signed[67:0] p1_inv_wire; wire signed[68:0] p2_inv_wire; wire signed[78:0] p3_inv_wire; wire signed[67:0] p4_inv_wire; wire signed[68:0] p5_inv_wire; wire signed[78:0] p6_inv_wire; wire signed[58:0] p7_inv_wire; wire signed[59:0] p8_inv_wire; wire signed[70:
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223 end 224 225 endmodule A.3.11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 pixel map.v ‘default_nettype none //////////////////////////////////////////////////////////////////////////////////////////// // pixel_map: This module performs the core perspective transformation // It computes (X, Y) = ((p1*x+p2*y+p3)/(p7*x+p8*y+p9), // (p4*x+p5*y+p6)/(p7*x+p8*y+p9)) given values pi (computed in // perspective_params.
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41 42 43 44 45 // internal registers for numerator and denominator computation // see perspective_params.
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87 .
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pixel_out <= BLACK; vga_in_wr <= 1; cur_state <= NEXT_PIXEL_ST; 133 134 135 end else begin pixel_out <= pixel_in; vga_in_wr <= 1; cur_state <= NEXT_PIXEL_ST; end 136 137 138 139 140 141 142 143 144 145 end endcase end endmodule A.3.12 1 2 3 4 5 6 7 8 9 audioManager.v ‘default_nettype none // Shawn Jain // Receives audio samples via FTDI UM245R USB-to-FIFO, stores to // onboard flash memory.
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output wire flash_oe_b, output wire flash_we_b, output wire flash_reset_b, output wire flash_byte_b, input wire flash_sts, output wire busy, 31 32 33 34 35 36 37 // USB I/O input wire [7:0] data, // the data pins from the USB fifo input wire rxf, // the rxf pin from the USB fifo output wire rd // the rd pin from the USB fifo (OUTPUT) 38 39 40 41 42 ); 43 44 45 // Playback addresses: parameter TRACK_LENGTH = 69000; // approx 1 sec 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
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77 78 79 80 81 82 83 reg writemode = 0; reg [15:0] wdata = 0; reg dowrite = 0; reg [22:0] raddr = 2; wire [15:0] frdata; reg doread = 0; // // // // // // 1=write mode; 0=read mode writeData 1=new data, write it readAddress readData 1=execute read 84 85 86 87 flash_manager fm( .clock(clock), .reset(reset), 88 // Interface I/O .writemode(writemode), .wdata(wdata), .dowrite(dowrite), .raddr(raddr), .frdata(frdata), .doread(doread), .busy(busy), 89 90 91 92 93 94 95 96 97 // Flash I/O .
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123 // Interface .out(out[7:0]), .newout(newout), .hold(hold) 124 125 126 127 128 ); 129 130 131 132 wire [3:0] hundreds; wire [3:0] tens; wire [3:0] ones; 133 134 135 136 137 138 139 BCD inputToBCD( .number({1’b0, audioSelector}), .hundreds(hundreds), .tens(tens), .ones(ones) ); 140 141 142 143 reg lastAudioTrigger; reg [2:0] third = 0; reg lastReady; 144 145 146 147 148 149 150 151 // Set of 4 addresses that represent a playback sequence // First track in bottom 23 bits[22:0].
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169 170 171 172 173 174 175 176 doread <= 1’b0; //dowrite <= 1’b0; // only write on new data // WATCH OUT!! if (newout) begin bytesRxed <= bytesRxed + 1; wdata <= {dataFromFifo, 8’b0};//{out, 8’b0}; dowrite <= 1’b1; end end 177 178 179 180 181 182 // if button is DOWN - scroll through addresses via buttons if (~writeSwitch) begin dowrite <= 1’b0; writemode <= 1’b0; doread <= 1’b1; 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 if (playing & ready) begin // REMOV
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215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 5: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, FIVE_INDEX}; 6: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SIX_INDEX}; 7: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SEVEN_INDEX}; 8: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, EIGHT_INDEX}; 9: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, NINE_INDEX}; default: playbackSeq <= {USED_IN
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261 262 263 264 265 266 267 268 269 270 271 272 else begin raddr <= playbackSeq[22:0] * TRACK_LENGTH; trackEndAddr <= playbackSeq[22:0] * TRACK_LENGTH + TRACK_LENGTH; end end end // if (~writeSwitch) end // if (startSwitch) else begin // TO ENABLE RESET: // writemode <= 1 // dowrite <= 0 // doread <= 0 // to be safe 273 274 275 276 277 278 279 280 // Reset First, Write Second, Read Later writemode <= 1’h1; doread <= 1’h0; dowrite <= 1’h0; end end // always @ endmodule A.3.13 1 2 binaryToDecimal.
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15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2: begin ones <= 2; tens <= 0; end 3: begin ones <= 3; tens <= 0; end 4: begin ones <= 4; tens <= 0; end 5: begin ones <= 5; tens <= 0; end 6: begin ones <= 6; tens <= 0; end 7: begin ones <= 7; tens <= 0; end 8: begin ones <= 8; tens <= 0; end 9: begin ones <= 9; tens <= 0; end 10: begin ones <= 0; tens <= 1; end 11: begin ones <= 1; tens <= 1; end 12: begin ones <= 2;
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61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 48: 49: 50: 51: 52: 53: 54: 55: 56: 57: 58: 59: 60: 61: 62: 63: 64: 65: 66: 67: 68: 69: 70: 71: 72: 73: 74: 75: 76: 77: 78: 79: 80: 81: 82: 83: 84: 85: 86: 87: 88: 89: 90: 91: 92: 93: begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin begin b
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107 108 109 110 111 112 113 114 115 116 117 94: begin ones 95: begin ones 96: begin ones 97: begin ones 98: begin ones 99: begin ones default: begin endcase hundreds <= 0; end endmodule <= 4; tens <= 5; tens <= 6; tens <= 7; tens <= 8; tens <= 9; tens ones <= 0; <= 9; end <= 9; end <= 9; end <= 9; end <= 9; end <= 9; end tens <= 0; end 118 119 120 // Note: a computational logic based binary to BCD is found at: // http://www.deathbylogic.
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end else if (counter == (fastMode ? 3:Hz)) begin oneHertz_enable <= 1’b1; counter <= 25’b0; end else begin counter <= counter + 1; oneHertz_enable <= 1’b0; end 16 17 18 19 20 21 22 23 24 end 25 26 27 endmodule A.3.16 1 2 3 Square.v // Shawn Jain // From Lab 4 // Generates a square wave that flips every Hz clock cycles 4 5 6 7 module Square #(parameter Hz = 27000000) ( input clock, reset, output reg square = 0); 8 9 wire oneHertz_enable; 10 11 12 13 14 15 16 ClockDivider #(.Hz(Hz)) Sqr ( .