Specifications

Known Design Marginality/Exceptions to Functional Specifications

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Advisory Read of Clock Control Registers on C28x Memory Map is EALLOW-Protected

Revision(s) Affected 0

Details Clock Control Registers on the C28x memory map are read-protected by EALLOW.

Workaround(s) Enable EALLOW before reading the Clock Control Registers on the C28x memory map.

Advisory VCU: First CRC Calculation May Not be Correct

Revision(s) Affected 0

Details Due to the internal power-up state of the VCU module, it is possible that the first CRC

result will be incorrect. This applies to the first result from each of the eight CRC

instructions. This condition can only occur after a power-on reset, but will not necessarily

occur on every power on. A warm reset will not cause this condition to reappear.

Workaround(s) The application can reset the internal VCU CRC logic by performing a CRC calculation

of a single byte in the initialization routine. This routine only needs to perform one CRC

calculation and can use any of the CRC instructions. At the end of this routine, clear the

VCU CRC result register to discard the result. An example is shown below.

_VCUcrc_reset

MOVZ XAR7, #0

VCRC8L_1 *XAR7

VCRCCLR

LRETR

This will be fixed in the next revision of the silicon.

Advisory UART: RTRIS Bit in the UARTRIS Register is Only Set When the Interrupt is

Enabled

Revision(s) Affected 0

Details The RTRIS (UART Receive Time-Out Raw Interrupt Status) bit in the UART Raw

Interrupt Status (UARTRIS) register should be set when a receive time-out occurs,

regardless of the state of the RTIM enable bit in the UART Interrupt Mask (UARTIM)

when a receive time-out occurs.

Workaround(s) For applications that require polled operation, the RTIM bit can be set while the UART

interrupt is disabled in the NVIC using the IntDisable(n) function in the StellarisWare™

Peripheral Driver Library, where n is 21, 22, or 49, depending on whether UART0,

UART1, or UART2 is used. With this configuration, software can poll the RTRIS bit, but

the interrupt is not reported to the NVIC.

F28M35x Concerto MCU Silicon Errata SPRZ357B– August 2011– Revised January 2012

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