Specifications

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Known Design Marginality/Exceptions to Functional Specifications

Advisory GPIO: GPIOs on Port C Do Not Toggle Correctly When Using the GPCTOGGLE

Revision(s) Affected 0

Details GPIOs on Port C do not toggle correctly when using the GPCTOGGLE register because

of a dependency on the state of GPIOs on Port A.

Workaround(s) Use GPCSET and GPCCLEAR registers or the GPCDAT register to toggle Port C

GPIOs.

This will be fixed in the next revision of the silicon.

Advisory C28x Flash: Code Executing From the C28x Subsystem Flash May be Subject to

Unnecessary 1-Cycle Delays

Revision(s) Affected 0

Details Code executing from the C28x Subsystem Flash may be subject to unnecessary 1-cycle

delays. This delay will not occur more often than once every 8 instructions for code that

is composed of linear 32-bit opcodes with no pipeline delays (worst case). In practice,

the unnecessary delay occurs rarely since the C28x uses both 16-bit opcodes and 32-bit

opcodes.

This delay can occur when Flash wait states are set to "3" and the prefetch mechanism

is enabled. This delay does not occur when the wait states are set to "2" or "1" with

prefetch enabled.

Workaround(s) None. This will be fixed in the next revision of the silicon.

Advisory C28x Clocking: EALLOW Protection of C28x Clocking Registers Prevents Read of

Registers

Revision(s) Affected 0

Details The EALLOW protection of the C28x clocking registers prevents reads to these registers

(reads return 0x0000) in addition to preventing writes to the registers (expected behavior

of EALLOW-protection) when EALLOW is not set.

Workaround(s) Prior to reading C28x clocking registers, the application code must first execute the

“EALLOW” command.

This will be fixed in the next revision of the silicon.

Advisory µDMA: No Transfer Completion Interrupt From SW Channels, Other Than

Channel 30

Revision(s) Affected 0

Details On a Concerto device, if any SW channel, other than Channel 30, is used for data

transfer, then there will be no completion interrupt generated on the µDMA interrupt line

when data transfer is done.

Workaround(s) The user must poll for the STATE field of the DMASTAT register of SW channel, used

for data transfer, to get set to “0x9” to detect completion of data transfer.

SPRZ357B– August 2011– Revised January 2012 F28M35x Concerto MCU Silicon Errata

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