Owners Manual

OPTIONAL DIGITAL CONVERTER 2 Module set that can user-fitted into any SLAM! and provide the following:
Analog to Digital Section:
Technology 128 x fS oversampling, Proprietary adaptive linear phase FIR (Sharc DSP) using 40
bit FP math. Sample rate always at 192K, "data rate" is user selectable.
Output AES/EBU 3 pin XLR male plus Word Clock / Super Clock BNC input for clock rate
Sample Rates 44.1K, 48K, 88.2K, 96K, or follows AES in or Word Clock or Super Clock input
Actual Sample Rate is ALWAYS 192K and then down-samples to any of the above data rates
Word Length 3 position toggle for 24, 20 or 16 bit data.
Dither & Noise Shaping Available for 20 or 16 bit output data, Two toggles, Dither is Triangular PDF.
Noise shaping is seventh order proprietary.
Anti-Alias Filtering 3 position toggle for 20K passive analog, 40K passive analog, or 20K Digital adaptive
FIR using 40 bit Floating Point Sharc DSP. Also uses a 90K FIR in analog modes.
Frequency response Follows above filters for -3dB points. See curves on page XYZ
Input stage Entirely passive into the A/D chip, or through tubes, limiters and transformers.
Dynamic range (passive mode) 120 dB
THD + N 96 dB (20-20K), 100 dB A Weighted
Jitter (3% TPDF injected into AES) no artifacts above -155 dB (essentially unmeasurable)
ASRC distortion & noise no artifacts above -155 dB (essentially unmeasurable)
Latency 44.1K = 190 samples = 4.3 mS = sound propagation of 4' 9" at sea level
48.0K = 195 samples = 4.1 mS = sound propagation of 4' 6" at sea level
88.2K = 251 samples = 2.8 mS = sound propagation of 3' 1" at sea level
96.0K = 262 samples = 2.7 mS = sound propagation of 3' 0" at sea level
Digital to Analog Section:
Technology 128 x fS oversampling, 64 level sigma delta architecture. DAC chip FIR filters
bypassed and instead use proprietary adaptive linear phase FIR (Sharc DSP) using 40
bit FP math. Extremely fast transient response and ultra-low jitter optimised design.
Input AES/EBU 3 pin XLR female plus Word Clock / Super Clock BNC input.
Sample Rates 44.1K, 48K, 88.2K, 96K
Actual Sample Rate is ALWAYS 192K and up-samples from any of the above data rates
Word Length Accepts 16 to 24 bit data.
Anti-Alias Filtering 3 position toggle for 20K passive analog, 40K passive analog, or 80K passive analog
Frequency response Follows above filters for -3dB points. See curves on page XYZ
Output stage fully balanced symetrical low cross-over distortion design capable of driving 50 ohm
loads without headroom loss. No capacitors (DC servos). Output is balanced +4 phone
jack and/or can be routed through tubes, limiters and transformers.
Dynamic range 115 dB
THD + N -117 dB (20-20K) @ -60, -104 at DFS
Jitter (3% TPDF injected) no artifacts above -155 dB (essentially unmeasurable)
ASRC distortion & noise no artifacts above -155 dB (essentially unmeasurable)
Latency 44.1K = 234 samples = 5.3 mS total A to D + D to A = 424 samples = 9.6 mS
48.0K = 237 samples = 4.9 mS total A to D + D to A = 432 samples = 9.0 mS
88.2K = 264 samples = 3.0 mS total A to D + D to A = 515 samples = 5.8 mS
96.0K = 269 samples = 2.8 mS total A to D + D to A = 531 samples = 5.5 mS
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