Data Sheet

Page 104
RFM95/96/97/98
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WIRELESS & SENSING PRELIMINARY DATASHEET
Name
(Address)
Bits
Variable Name
Mode
Reset
LoRa
TM
Description
RegLna
(0x0C)
7-5
LnaGain
rwx
0x01
LNA gain setting:
000  not used
001  G1 = maximum gain
010  G2
011  G3
100  G4
101  G5
110  G6 = minimum gain
111  not used
4-3
LnaBoostLf
rw
0x00
Low Frequency (RFI_LF) LNA current adjustment
00  Default LNA current
Other  Reserved
2
reserved
rw
0x00
reserved
1-0
LnaBoostHf
rw
0x00
High Frequency (RFI_HF) LNA current adjustment
00  Default LNA current
11  Boost on, 150% LNA current
Lora page registers
RegFifoAddrPtr
(0x0D)
7-0
FifoAddrPtr
rw
0x00
SPI interface address pointer in FIFO data buffer.
RegFifoTxBaseAd
dr
(0x0E)
7-0
FifoTxBaseAddr
rw
0x80
write base address in FIFO data buffer for TX modulator
RegFifoRxBaseAd
dr
(0x0F)
7-0
FifoRxBaseAddr
rw
0x00
read base address in FIFO data buffer for RX demodulator
RegFifoRxCurrent
Addr
(0x10)
7-0
FifoRxCurrentAddr
r
n/a
Start address (in data buffer) of last packet received
RegIrqFlagsMask
(0x11)
7
RxTimeoutMask
rw
0x00
Timeout interrupt mask: setting this bit masks the corresponding
IRQ in RegIrqFlags
6
RxDoneMask
rw
0x00
Packet reception complete interrupt mask: setting this bit masks
the corresponding IRQ in RegIrqFlags
5
PayloadCrcErrorMask
rw
0x00
Payload CRC error interrupt mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
4
ValidHeaderMask
rw
0x00
Valid header received in Rx mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
3
TxDoneMask
rw
0x00
FIFO Payload transmission complete interrupt mask: setting this
bit masks the corresponding IRQ in RegIrqFlags
2
CadDoneMask
rw
0x00
CAD complete interrupt mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
1
FhssChangeChannelM
ask
rw
0x00
FHSS change channel interrupt mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
0
CadDetectedMask
rw
0x00
Cad Detected Interrupt Mask: setting this bit masks the
corresponding IRQ in RegIrqFlags