Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
3.9.6 SHA Accelerator
ESP32-S3 integrates an SHA accelerator, which is a hardware device that speeds up SHA algorithm significantly.
The SHA Accelerator supports the following features:
• All the hash algorithms introduced in FIPS PUB 180-4 Spec.
– SHA-1
– SHA-224
– SHA-256
– SHA-384
– SHA-512
– SHA-512/224
– SHA-512/256
– SHA-512/t
• Two working modes
– Typical SHA
– DMA-SHA
• interleaved function when working in Typical SHA working mode
• Interrupt function when working in DMA-SHA working mode
For more information, please refer to Chapter SHA Accelerator (SHA) in ESP32-S3 Technical Reference
Manual.
3.9.7 AES Accelerator
ESP32-S3 integrates an Advanced Encryption Standard (AES) Accelerator, which is a hardware device that
speeds up AES Algorithm significantly. The AES Accelerator supports the following features:
• Typical AES working mode
– AES-128/AES-256 encryption and decryption
• DMA-AES working mode
– AES-128/AES-256 encryption and decryption
– Block cipher mode
* ECB (Electronic Codebook)
* CBC (Cipher Block Chaining)
* OFB (Output Feedback)
* CTR (Counter)
* CFB8 (8-bit Cipher Feedback)
* CFB128 (128-bit Cipher Feedback)
– Interrupt on completion of computation
For more information, please refer to Chapter AES Accelerator (AES) in ESP32-S3 Technical Reference
Manual.
Espressif Systems 44
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ESP32-S3 Series Datasheet v1.2