Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
• Encryption and decryption functions jointly determined by registers configuration, eFuse parameters, and
boot mode
For more information, please refer to Chapter External Memory Encryption and Decryption (XTS_AES) in
ESP32-S3 Technical Reference Manual.
3.9.2 Secure Boot
Secure Boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature) can
be booted.
3.9.3 HMAC Accelerator
The Hash-based Message Authentication Code (HMAC) module computes Message Authentication Codes
(MACs) using Hash algorithm and keys as described in RFC 2104. The HMAC Accelerator in ESP32-S3 supports
the following features:
• Standard HMAC-SHA-256 algorithm
• Hash result only accessible by configurable hardware peripheral (in downstream mode)
• Compatible to challenge-response authentication algorithm
• Generates required keys for the Digital Signature (DS) peripheral (in downstream mode)
• Re-enables soft-disabled JTAG (in downstream mode)
For more information, please refer to Chapter HMAC Accelerator (HMAC) in ESP32-S3 Technical Reference
Manual.
3.9.4 Digital Signature
A Digital Signature is used to verify the authenticity and integrity of a message using a cryptographic algorithm.
The Digital Signature (DS) in ESP32-S3 supports the following features:
• RSA Digital Signatures with key length up to 4096 bits
• Encrypted private key data, only decryptable by DS peripheral
• SHA-256 digest to protect private key data against tampering by an attacker
For more information, please refer to Chapter Digital Signature (DS) in ESP32-S3 Technical Reference
Manual.
3.9.5 World Controller
The ESP32-S3 can divide the hardware and software resources into a Secure World and a Non-Secure World to
prevent sabotage or access to device information. Switching between the two worlds is performed by the World
Controller, which supports the following features:
• Control of the CPU switching between secure and non-secure worlds
• Control of 15 DMA peripherals switching between secure and non-secure worlds
• Record of CPU’s world switching logs
• Shielding of the CPU’s NMI interrupt
Espressif Systems 43
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ESP32-S3 Series Datasheet v1.2