Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
For more information, please refer to Chapter System Timer (SYSTIMER) in ESP32-S3 Technical Reference
Manual.
3.8.3 Watchdog Timers
The ESP32-S3 contains three watchdog timers: one in each of the two timer groups (called Main System
Watchdog Timers, or MWDT) and one in the RTC Module (called the RTC Watchdog Timer, or RWDT).
During the flash boot process, RWDT and the first MWDT are enabled automatically in order to detect and
recover from booting errors.
Watchdog timers have the following features:
• Four stages, each with a programmable timeout value. Each stage can be configured, enabled and
disabled separately
• Interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or
system reset for RWDT upon expiry of each stage
• 32-bit expiry counter
• Write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
• Flash boot protection
If the boot process from an SPI flash does not complete within a predetermined period of time, the
watchdog will reboot the entire main system.
For more information, please refer to Chapter Watchdog Timers in ESP32-S3 Technical Reference Manual.
3.8.4 XTAL32K Watchdog Timers
Interrupt and WakeUp
When the XTAL32K watchdog timer detects the oscillation failure of XTAL32K_CLK, an oscillation failure interrupt
RTC_XTAL32K_DEAD_INT (for interrupt description, please refer to ESP32-S3 Technical Reference Manual) is
generated. At this point, the CPU will be woken up if in Light-sleep mode or Deep-sleep mode.
BACKUP32K_CLK
Once the XTAL32K watchdog timer detects the oscillation failure of XTAL32K_CLK, it replaces XTAL32K_CLK
with BACKUP32K_CLK (with a frequency of 32 kHz or so) derived from RTC_CLK as RTC’s SLOW_CLK, so as
to ensure proper functioning of the system.
For more information, please refer to Chapter XTAL32K Watchdog Timers (XTWDT) in ESP32-S3 Technical
Reference Manual.
3.9 Cryptography/Security Components
3.9.1 External Memory Encryption and Decryption
ESP32-S3 integrates an External Memory Encryption and Decryption module that complies with the XTS-AES
standard. It supports the following features:
• General XTS_AES algorithm, compliant with IEEE Std 1619-2007
• Software-based manual encryption
• High-speed auto encryption, without software’s participation
• High-speed auto decryption, without software’s participation
Espressif Systems 42
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ESP32-S3 Series Datasheet v1.2