Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
– A control pipe consists of two channels (IN and OUT), as IN and OUT transactions must be handled
separately. Only Control transfer type is supported.
– Each of the other seven channels is dynamically configurable to be IN or OUT, and supports Bulk,
Isochronous, and Interrupt transfer types.
• All channels share an RX FIFO, non-periodic TX FIFO, and periodic TX FIFO. The size of each FIFO is
configurable.
For more information, please refer to Chapter USB On-The-Go (USB) in ESP32-S3 Technical Reference
Manual.
3.5.12 USB Serial/JTAG Controller
ESP32-S3 integrates a USB Serial/JTAG controller that supports the following features:
• USB Full-speed device.
• Can be configured to either use internal USB PHY of ESP32-S3 or external PHY via GPIO matrix.
• Fixed function device, hardwired for CDC-ACM (Communication Device Class - Abstract Control Model)
and JTAG adapter functionality.
• 2 OUT Endpoints, 3 IN Endpoints in addition to Control Endpoint 0; Up to 64-byte data payload size.
• Internal PHY, so no or very few external components needed to connect to a host computer.
• CDC-ACM adherent serial port emulation is plug-and-play on most modern OSes.
• JTAG interface allows fast communication with CPU debug core using a compact representation of JTAG
instructions.
• CDC-ACM supports host controllable chip reset and entry into download mode.
For more information, please refer to Chapter USB Serial/JTAG Controller (USB_SERIAL_JTAG) in ESP32-S3
Technical Reference Manual.
3.5.13 Motor Control PWM (MCPWM)
ESP32-S3 integrates two MCPWM that can be used to drive digital motors and smart light. Each MCPWM
peripheral has one clock divider (prescaler), three PWM timers, three PWM operators, and a capture module.
PWM timers are used for generating timing references. The PWM operators generate desired waveform based
on the timing references. Any PWM operator can be configured to use the timing references of any PWM timers.
Different PWM operators can use the same PWM timer’s timing references to produce related PWM signals.
PWM operators can also use different PWM timers’ values to produce the PWM signals that work alone. Different
PWM timers can also be synchronized together.
For more information, please refer to Chapter Motor Control PWM (MCPWM) in ESP32-S3 Technical Reference
Manual.
3.5.14 SD/MMC Host Controller
ESP32-S3 has an SD/MMC Host Controller with the following features:
• Secure Digital (SD) memory version 3.0 and version 3.01
• Secure Digital I/O (SDIO) version 3.0
• Consumer Electronics Advanced Transport Architecture (CE-ATA) version 1.1
• Multimedia Cards (MMC version 4.41, eMMC version 4.5 and version 4.51)
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ESP32-S3 Series Datasheet v1.2