Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
For more information, please refer to Chapter Clock Glitch Detection in ESP32-S3 Technical Reference
Manual.
3.5 Digital Peripherals
3.5.1 IO MUX and GPIO Matrix
GPIO Matrix Features
• A full-switching matrix between the peripheral input/output signals and the GPIO pins
• 175 digital peripheral input signals can be sourced from the input of any GPIO pins
• The output of any GPIO pins can be from any of the 184 digital peripheral output signals
• Supports signal synchronization for peripheral inputs based on APB clock bus
• Provides input signal filter
• Supports sigma delta modulated output
• Supports GPIO simple input and output
IO MUX Features
• Provides one configuration register IO_MUX_GPIOn_REG for each GPIO pin. The pin can be configured to
– perform GPIO function routed by GPIO matrix.
– or perform direct connection bypassing GPIO matrix.
• Supports some high-speed digital signals (SPI, JTAG, UART) bypassing GPIO matrix for better
high-frequency digital performance. In this case, IO MUX is used to connect these pins directly to
peripherals.
RTC IO MUX Features
• Controls low power feature of 22 RTC GPIO pins.
• Controls analog functions of 22 RTC GPIO pins.
• Redirects 22 RTC input/output signals to RTC system.
For more information, please refer to Chapter IO MUX and GPIO Matrix (GPIO, IO MUX) in ESP32-S3 Technical
Reference Manual.
3.5.2 Serial Peripheral Interface (SPI)
ESP32-S3 features four SPI interfaces (SPI0, SPI1, SPI2 and SPI3). SPI0 and SPI1 can be configured to operate
in SPI memory mode; SPI2 and SPI3 can be configured to operate in general-purpose SPI mode.
• SPI Memory mode
In SPI memory mode, SPI0 and SPI1 interface with external SPI memory. Data transmission is in multiples
of bytes. Up to 8-line SDR/DDR (Single Data Rate/Double Data Rate) reads and writes are supported. The
clock frequency is configurable to a maximum of 120 MHz for OPI SDR/DDR mode.
• SPI2 Generalpurpose SPI (GPSPI) mode
SPI2 can operate in master and slave modes. The master mode supports two-line full-duplex
communication and single-/two-/four-/eight-line half-duplex communication. The slave mode supports
two-line full-duplex communication and single-/two-/four-line half-duplex communication. The host’s clock
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ESP32-S3 Series Datasheet v1.2