Datasheet

3 Functional Description
The temperature sensor has a range of –20 °C to 110 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors such as microcontroller clock frequency or
I/O load. Generally, the chip’s internal temperature is higher than the ambient temperature.
3.3.3 Touch Sensor
ESP32-S3 has 14 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the
GPIOs with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit
allow relatively small pads to be used. Arrays of pads can also be used, so that a larger area or more points can
be detected. The touch sensing performance can be further enhanced by the waterproof design and digital
filtering feature.
3.4 System Components
3.4.1 Reset and Clock
ESP32-S3 provides four reset levels, namely CPU Reset, Core Reset, System Reset, and Chip Reset.
• Support four reset levels:
– CPU Reset: only resets CPUx core. CPUx can be CPU0 or CPU1 here. Once such reset is released,
programs will be executed from CPUx reset vector. Each CPU core has its own reset logic. If CPU
Reset is from CPU0, the sensitive registers will be reset, too.
– Core Reset: resets the whole digital system except RTC, including CPU0, CPU1, peripherals, Wi-Fi,
Bluetooth
®
LE (BLE), and digital GPIOs.
– System Reset: resets the whole digital system, including RTC.
– Chip Reset: resets the whole chip.
• Support software reset and hardware reset:
– Software reset is triggered by CPUx configuring its corresponding registers.
– Hardware reset is directly triggered by the circuit.
For detailed information, please refer to Chapter Reset and Clock in ESP32-S3 Technical Reference
Manual.
3.4.2 Interrupt Matrix
The interrupt matrix embedded in ESP32-S3 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts, to timely inform CPU0 or CPU1 to process the interrupts once the interrupt signals
are generated. The Interrupt Matrix has the following features:
• 99 peripheral interrupt sources as input
• Generate 26 peripheral interrupts to CPU0 and 26 peripheral interrupts to CPU1 as output. Note that the
remaining six CPU0 interrupts and six CPU1 interrupts are internal interrupts.
• Disable CPU non-maskable interrupt (NMI) sources
• Query current interrupt status of peripheral interrupt sources
For detailed information, please refer to Chapter Interrupt Matrix (INTERRUPT) in ESP32-S3 Technical Reference
Manual.
Espressif Systems 29
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ESP32-S3 Series Datasheet v1.2