Datasheet

3 Functional Description
• Instruction cache: 16 KB (one bank) or 32 KB (two banks)
Data cache: 32 KB (one bank) or 64 KB (two banks)
• Instruction cache: four-way or eight-way set associative
Data cache: four-way set associative
• Block size of 16 bytes or 32 bytes for both instruction cache and data cache
• Pre-load function
• Lock function
• Critical word first and early restart
3.1.6 eFuse Controller
ESP32-S3 contains a 4-Kbit eFuse to store parameters, which are burned and read by an eFuse Controller. The
eFuse Controller has the following features:
• 4 Kbits in total, with 1792 bits reserved for users, e.g., encryption key and device ID
• One-time programmable storage
• Configurable write protection
• Configurable read protection
• Various hardware encoding schemes to protect against data corruption
For detailed information, please refer to Chapter eFuse Controller in ESP32-S3 Technical Reference
Manual.
3.1.7 Processor Instruction Extensions
The ESP32-S3 contains a series of new extended instruction set in order to improve the operation efficiency of
specific AI and DSP (Digital Signal Processing) algorithms. The Processor Instruction Extensions (PIE) has the
following features:
• 128-bit new general-purpose registers
• 128-bit vector operations, e.g., complex multiplication, addition, subtraction, multiplication, shifting,
comparison, etc
• Data handling instructions and load/store operation instructions combined
• Non-aligned 128-bit vector data
• Saturation operation
3.2 RTC and LowPower Management
3.2.1 Power Management Unit (PMU)
With the use of advanced power-management technologies, ESP32-S3 can switch between different power
modes.
• Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.
• Modemsleep mode: The CPU is operational and the clock speed can be reduced. The wireless
baseband and radio are disabled, but wireless connection can remain active.
Espressif Systems 27
Submit Documentation Feedback
ESP32-S3 Series Datasheet v1.2