Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
• External RAM mapped into 32 MB data space as individual blocks of 64 KB. 8-bit, 16-bit, 32-bit, and
128-bit reads and writes are supported. External flash can also be mapped into 32 MB data space as
individual blocks of 64 KB, but only supporting 8-bit, 16-bit, 32-bit and 128-bit reads.
Note:
After ESP32-S3 is initialized, firmware can customize the mapping of external RAM or flash into the CPU address space.
3.1.4 Address Mapping Structure
Figure 7: Address Mapping Structure
Note:
The memory space with gray background is not available to users.
3.1.5 Cache
ESP32-S3 has an instruction cache and a data cache shared by the two CPU cores. Each cache can be
partitioned into multiple banks and has the following features:
Espressif Systems 26
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ESP32-S3 Series Datasheet v1.2